NXP Semiconductors MPC5644A, Reference Manual, Page: 32 / 1735

Introduction
MPC5644A Microcontroller Reference Manual, Rev. 6
32 Freescale Semiconductor
1.4 Feature summary
• 150 MHz e200z4 Power Architecture core
— Variable length instruction encoding (VLE)
— Superscalar architecture with 2 execution units
— Up to 2 integer or floating point instructions per cycle
— Up to 4 multiply and accumulate operations per cycle
• Memory organization
— 4 MB on-chip flash memory with ECC and Read While Write (RWW)
— 192 KB on-chip SRAM with standby functionality (32 KB) and ECC
— 8 KB instruction cache (with line locking), configurable as 2- or 4-way
— 14 + 3 KB eTPU code and data RAM
— 5

4 crossbar switch (XBAR)
— 24-entry MMU
— External Bus Interface (EBI) with slave and master port
• Fail Safe Protection
— 16-entry Memory Protection Unit (MPU)
— CRC unit with 3 sub-modules
— Junction temperature sensor
• Interrupts
— Configurable interrupt controller (with NMI)
— 64-channel DMA
• Serial channels
— 3

eSCI
— 3

DSPI (2 of which support downstream Micro Second Channel [MSC])
— 3

FlexCAN with 64 messages each
— 1

FlexRay module (V2.1) up to 10 Mbit/s with dual or single channel and 128 message
objects and ECC
• 1

eMIOS
— 24 unified channels
• 1

eTPU2 (second generation eTPU)
— 32 standard channels
— 1

reaction module (6 channels with three outputs per channel)
• 2 enhanced queued analog-to-digital converters (eQADCs)
— Forty 12-bit input channels (multiplexed on 2 ADCs); expandable to 56 channels with external
multiplexers
— 6 command queues
— Trigger and DMA support