External Bus Interface (EBI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
327
Figure 14-35. 32-bit Write to MCU with DBM=1
14.5.2.10 Calibration bus operation
Some devices with this EBI have a second external bus, intended for calibration use. This bus consists of
a second set of the same signals present on the Primary external bus, except that arbitration, (and optionally
other signals also) are excluded. Both busses can be supported with one EBI block, by using the calibration
chip-selects to steer accesses to the calibration bus instead of the primary external bus.
Since the calibration bus has no arbitration signals, the arbitration on the primary bus controls accesses on
the calibration bus as well, and no external master accesses can be performed on the calibration bus.
Accesses cannot be performed in parallel on both external busses. However, back-to-back accesses can
switch from one bus to the other, as determined by the type of chip-select each address matches.
The timing diagrams and protocol for the calibration bus is identical to the primary bus, except that some
signals are missing on the calibration bus. See the device-specific documentation for the calibration bus
signal list for a particular MCU.
There is an inherent dead cycle between a calibration chip-select access and a non-calibration access
(chip-select or non-chip-select), just like the one between accesses to two different non-calibration
chip-selects (described in
Section 14.5.2.4.3, Back-to-Back accesses
).
shows an example of a non-calibration chip-select read access followed by a calibration
chip-select read access. Note that this figure is identical to
, except the CSy is replaced by
CAL_CSy. Timing for other cases on calibration bus can similarly be derived from other figures in this
document (by replacing CS with CAL_CS).
DATA is valid
CLKOUT
RD_WR
BDIP
ADDR[3:31]
DATA[0:15]
TS (output)
Minimum
3 wait states
TA (input)
DATA is valid
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