NXP Semiconductors MPC5644A, Reference Manual, Page: 1313 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1313
• all transmit commands must have the same PCSn bits programming
• the DSPI_CTARs, selected by transmit commands, must be programmed with the same transfer
attributes. Only field FMSZ can be programmed differently in these DSPI_CTARs.
NOTE
It is mandatory to fill the TXFIFO with the number of entries that will be
concatenated together under one PCS assertion for both master and slave
before the TXFIFO becomes empty. For example, while transmitting in
master mode, it should be ensured that the last entry in the TXFIFO, after
which TXFIFO becomes empty, must have the CONT bit in command
frame as deasserted (i.e. CONT bit = 0).While operating in slave mode, it
should be ensured that when the last-entry in the TXFIFO is comp.letely
transmited (i.e. the corresponding TCF flag is asserted and TXFIFO is
empty) the slave should be deselected for any further serial communication;
else an underflow error occurs.
30.9.7 Continuous serial communications clock
The DSPI provides the option of generating a continuous SCK signal for slave peripherals that require a
continuous clock.
Continuous SCK is enabled by setting bit DSPI_MCR[CONT_SCKE]. Continuous SCK is valid in all
configurations.
Continuous SCK is only supported for CPHA = 1. Clearing CPHA is ignored if bit
DSPI_MCR[CONT_SCKE] is set. Continuous SCK is supported for Modified Transfer Format.
Clock and transfer attributes for the Continuous SCK mode are set according to the following rules:
• The TX FIFO must be cleared before initiating any SPI configuration transfer.
• When the DSPI is in SPI configuration, CTAR0 shall be used initially. At the start of each SPI
frame transfer, the CTAR specified by the CTAS for the frame should be CTAR0.
• When the DSPI is in DSI configuration, the CTAR specified by the DSICTAS field shall be used
at all times.
• When the DSPI is in CSI configuration, the CTAR selected by the DSICTAS field shall be used
initially. At the start of an SPI frame transfer, the CTAR specified by the CTAS value (which is
CTAR0) for the frame shall be used. At the start of a DSI frame transfer, the CTAR specified by
the DSICTAS field shall be used.
• In all configurations, the currently selected DSPI_CTAR remains in use until the start of a frame
with a different DSPI_CTAR specified, or the Continuous SCK mode is terminated.
It is recommended to keep the baud rate the same while using the Continuous SCK. Switching clock
polarity between frames while using Continuous SCK can cause errors in the transfer. Continuous SCK
operation is not guaranteed if the DSPI is put into the External Stop mode or Module Disable mode.
Enabling Continuous SCK disables the PCS to SCK delay and the Delay after Transfer (t
DT
) is fixed to
one SCK cycle. When TSB configuration is enabled the t
DT
is programmable from 1 to 65 SCK cycles.
Figure 30-48 shows timing diagram for Continuous SCK format with Continuous Selection disabled.