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Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
1046
Freescale Semiconductor
Table 25-22.
EQADC
SSI Control Register (
EQADC
_SSICR) field description
Field
Description
21-23
MDT[0:2]
Minimum Delay after Transmission
MDT field defines the minimum delay after transmission time (t
MDT
) expressed in serial clock
(FCK) periods. t
MDT
is minimum time SDS should be kept negated between two consecutive
lists the minimum delay after transfer time according to
how MDT is set.
The MDT field must only be written when the serial transmissions from the EQADC SSI are
disabled - See ESSIE field in
Section 25.5.2.1, EQADC Module Configuration Register
.
28-31
BR[0:3]
Baud Rate Field
The BR field selects system clock divide factor as shown in
. The baud clock is
calculated by dividing the system clock by the clock divide factor specified with the BR field.
The BR field must only be written when the EQADC SSI is disabled - See ESSIE field in
Section 25.5.2.1, EQADC Module Configuration Register (EQADC_MCR)
Table 25-23. Minimum Delay After Transmission (t
MDT
) Time
MDT
t
MDT
(FCK period)
0b000
1
0b001
2
0b010
3
0b011
4
0b100
5
0b101
6
0b110
7
0b111
8
Table 25-24. System Clock Divide Factor for Baud Clock
BR[0:3]
System Clock Divide Factor
1
0b0000
2
0b0001
3
0b0010
4
0b0011
5
0b0100
6
0b0101
7
0b0110
8
0b0111
9
Summary of Contents for MPC5644A
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Page 24: ...MPC5644A Microcontroller Reference Manual Rev 6 24 Freescale Semiconductor...
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Page 52: ...Introduction MPC5644A Microcontroller Reference Manual Rev 6 52 Freescale Semiconductor...
Page 56: ...Memory Map MPC5644A Microcontroller Reference Manual Rev 6 56 Freescale Semiconductor...
Page 1228: ...Decimation Filter MPC5644A Microcontroller Reference Manual Rev 6 1228 Freescale Semiconductor...
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