NXP Semiconductors MPC5644A, Reference Manual, Page: 1272 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1272 Freescale Semiconductor
30.8.2.6 DSPI DMA/Interrupt Request Select and Enable Register (DSPI_RSER)
The DSPI_RSER controls DMA and interrupt requests. Do not write to the DSPI_RSER while the DSPI
is in the Running state.
14
RFDF
Receive FIFO Drain Flag
The RFDF bit provides a method for the DSPI to request that entries be removed from the RX FIFO.
The bit is set while the RX FIFO is not empty. The RFDF bit can be cleared by writing 1 to it or by
acknowledgement from the DMA controller when the RX FIFO is empty.
0 RX FIFO is empty
1 RX FIFO is not empty
15 Reserved.
16–20
TXCTR
TX FIFO Counter
The TXCTR field indicates the number of valid entries in the TX FIFO. The TXCTR is incremented
every time the DSPI _PUSHR is written. The TXCTR is decremented every time a SPI command is
executed and the SPI data is transferred to the shift register.
20–23
TXNXTPTR
Transmit Next Pointer
The TXNXTPTR field indicates which TX FIFO Entry is transmitted during the next transfer. The
TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to the shift register.
See
Section 30.9.10.4, Transmit FIFO underflow interrupt request , for more details.
24–27
RXCTR
RX FIFO Counter
The RXCTR field indicates the number of entries in the RX FIFO. The RXCTR is decremented every
time the DSPI _POPR is read. The RXCTR is incremented every time data is transferred from the
shift register to the RX FIFO.
28–31
POPNXTPT
R
Pop Next Pointer
The POPNXTPTR field contains a pointer to the RX FIFO entry that will be returned when the
DSPI_POPR is read. The POPNXTPTR is updated when the DSPI_POPR is read. See
Section 30.9.2.5, Receive first-in first-out (RX FIFO) buffering mechanism , for more details.
Address: DSP 0x30
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
TC
F_R
E
0 0
EOQFRE
TFUFRE
0
TF
FF
RE
TF
FF
DI
RS
0
DPE
F
R
E
S
PEFRE
DD
IF
R
E
RFOFRE
0
RFDFRE
RFDFDIRS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 30-11. DSPI DMA/Interrupt Request Select and Enable Register (DSPI_RSER)
Table 30-12. DSPI_SR field description (continued)
Field Description