NXP Semiconductors MPC5644A, Reference Manual, Page: 1319 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1319
The DSPI module also provides a global interrupt request line, which is asserted when any of individual
interrupt requests lines is asserted.
30.9.10.1 End of queue interrupt request
The End of Queue Request indicates that the end of a transmit queue is reached. The End of Queue Request
is generated when the EOQ bit in the executing SPI command is set and bit DSPI_RSER[EOQFRE] is set.
30.9.10.2 Transmit FIFO fill interrupt or DMA request
The Transmit FIFO Fill Request indicates that the TX FIFO is not full. The Transmit FIFO Fill Request is
generated when the number of entries in the TX FIFO is less than the maximum number of possible entries,
and the TFFFRE bit in the DSPI_RSER is set. The TFFFDIRS bit in the DSPI_RSER selects whether a
DMA request or an interrupt request is generated.
30.9.10.3 Transfer complete interrupt request
The Transfer Complete Request indicates the end of the transfer of a serial frame. The Transfer Complete
Request is generated at the end of each frame transfer when the TCF_RE bit is set in the DSPI_RSER.
30.9.10.4 Transmit FIFO underflow interrupt request
The Transmit FIFO Underflow Request indicates that an underflow condition in the TX FIFO has
occurred. The transmit underflow condition is detected only for the DSPI, operating in slave mode and SPI
configuration. The TFUF bit is set when the TX FIFO of a DSPI is empty, and a transfer is initiated from
an external SPI master. If the TFUF bit is set while the TFUFRE bit in the DSPI_RSER is set, an interrupt
request is generated.
30.9.10.5 Receive FIFO drain interrupt or DMA request
The Receive FIFO Drain Request indicates that the RX FIFO is not empty. The Receive FIFO Drain
Request is generated when the number of entries in the RX FIFO is not zero, and the RFDFRE bit in the
DSPI_RSER is set. The RFDFDIRS bit in the DSPI_RSER selects whether a DMA request or an interrupt
request is generated.
30.9.10.6 Receive FIFO overflow interrupt request
The Receive FIFO Overflow Request indicates that an overflow condition in the RX FIFO has occurred.
A Receive FIFO Overflow request is generated when RX FIFO and shift register are full and a transfer is
initiated. The RFOFRE bit in the DSPI_RSER must be set for the interrupt request to be generated.
Depending on the state of the ROOE bit in the DSPI_MCR, the data from the transfer that generated the
overflow is either ignored or shifted in to the shift register. If the ROOE bit is set, the incoming data is
shifted in to the shift register. If the ROOE bit is cleared, the incoming data is ignored.