NXP Semiconductors MPC5644A, Reference Manual, Page: 1550 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
1550 Freescale Semiconductor
NOTE
The CC will not access any locations outside the message buffer data field
boundaries given by
Table 33-101 .
Figure 33-128. Message buffer data field structure
The message buffer data field is located in the FlexRay memory area; thus, the CC has no means to control
application write access to the field. To ensure data consistency, the application must follow a write and
read access scheme.
33.6.5.3.1 Message buffer data field read access
For transmit message buffers, the CC will not modify the content of the Message Buffer Data Field. Thus
the application can read back the data at any time without any impact on data consistency.
For receive message buffers the application must lock the related receive message buffer and retrieve the
message buffer header index from the
Message Buffer Index Registers (FR_MBIDXRn) . While the
message buffer is locked, the CC will not update the Message Buffer Data Field.
For receive FIFOs, the application can read the message buffer indicated by the Receive FIFO A Read
Index Register (FR_RFARIR) or the Receive FIFO B Read Index Register (FR_RFBRIR) when the related
fill levels in the Receive FIFO Fill Level and POP Count Register (FR_RFFLPCR) indicate an non-empty
FIFO.
33.6.5.3.2 Message buffer data field write access
For receive message buffers, receive shadow buffers, and receive FIFOs, the application must not write to
the message buffer data field.
Table 33-101. Message buffer data field minimum length
Physical message buffer assigned to Minimum length defined by
Individual Message Buffer in Segment 1 FR_MBDSR[MBSEG1DS]
Receive Shadow Buffer in Segment 1 FR_MBDSR[MBSEG1DS]
Individual Message Buffer in Segment 2 FR_MBDSR[MBSEG2DS]
Receive Shadow Buffer in Segment 2 FR_MBDSR[MBSEG2DS]
Receive FIFO for channel A FR_RFDSR[ENTRY_SIZE] (FR_RFWMSR[SEL] = 0)
Receive FIFO for channel B FR_RFDSR[ENTRY_SIZE] (FR_RFWMSR[SEL] = 1)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0x0 DATA0 / MID0 / NMV0 DATA1 / MID1 / NMV1
0x2 DATA2 / NMV2 DATA3 / NMV3
... ... ...
0xN-2 DATA N-2 DATA N-1