NXP Semiconductors MPC5644A, Reference Manual, Page: 1507 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1507
33.5.2.58 Receive FIFO A Read Index Register (FR_RFARIR)
This register provides the message buffer header index of the next available FIFO A entry that the
application can read.
NOTE
If the FIFO is empty, the RDIDX field points to an physical message buffer
with invalid content.
33.5.2.59 Receive FIFO B Read Index Register (FR_RFBRIR)
This register provides the message buffer header index of the next available FIFO B entry that the
application can read.
Base + 0x008C
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 RDIDX
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 33-59. Receive FIFO A Read Index Register (FR_RFARIR)
Table 33-67. FR_RFARIR field description
Field Description
RDIDX Read Index — This field provides the message buffer header index of the next available FIFO
message buffer that the application can read.
If the old style FIFO mode is configured (FR_MCR[FIMD] = 0), the CC updates this index by 1 entry,
when the application writes to the FAFAIF flag in the
Global Interrupt Flag and Enable Register
(FR_GIFER) .
If the new style FIFO mode is configured (FR_MCR[FIMD] = 1), the CC updates this index by PCA
entries, when the application writes to the
Receive FIFO Fill Level and POP Count Register
(FR_RFFLPCR) .
Base + 0x008E
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 RDIDX
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 33-60. Receive FIFO B Read Index Register (FR_RFBRIR)
Table 33-68. FR_RFBRIR field description
Field Description
RDIDX Read Index — This field provides the message buffer header index of the next available FIFO
message buffer that the application can read.