NXP Semiconductors MPC5644A, Reference Manual, Page: 172 / 1735

Enhanced Direct Memory Access Controller (eDMA)
MPC5644A Microcontroller Reference Manual, Rev. 6
172 Freescale Semiconductor
8.4 Functional description
This section provides an overview of the microarchitecture and functional operation of the eDMA block.
The eDMA module is partitioned into two major modules: the DMA engine and the transfer control
descriptor local memory. The DMA engine is further partitioned into four submodules, which are detailed
below.
• DMA engine
— Address path: This module implements registered versions of two channel transfer control
descriptors: channel x and channel y, and is responsible for all the master bus address
calculations. All the implemented channels provide the same functionality. This hardware
structure allows the data transfers associated with one channel to be pre-empted after the
completion of a read/write sequence if a higher priority channel service request is asserted
while the first channel is active. After a channel is activated, it runs until the minor loop is
completed unless pre-empted by a higher priority channel. This capability provides a
mechanism (optionally enabled by EDMA_CPR
n [ECP]) where a large data move operation
can be pre-empted to minimize the time another channel is blocked from execution.
— When another channel is activated, the contents of its transfer control descriptor is read from
the local memory and loaded into the registers of the other address path channel{x,y}. After
the inner minor loop completes execution, the address path hardware writes the new values for
the TCD
n .{SADDR, DADDR, CITER} back into the local memory. If the major iteration
count is exhausted, additional processing is performed, including the final address pointer
updates, reloading the TCDn.CITER field, and a possible fetch of the next TCD
n from memory
as part of a scatter-gather operation.
— Data path: This module implements the actual bus master read/write datapath. It includes 32
bytes of register storage (matching the maximum transfer size) and the necessary mux logic to
support any required data alignment. The system read data bus is the primary input, and the
system write data bus is the primary output.
254 /
0x1C [30]
INT_MAJ Enable an interrupt when major iteration count completes
If this flag is set, the channel generates an interrupt request by setting the
appropriate bit in the EDMA_ERQH or EDMA_ERQL when the current major
iteration count reaches zero.
0 The end-of-major loop interrupt is disabled.
1 The end-of-major loop interrupt is enabled.
255 /
0x1C [31]
START Channel start
If this flag is set the channel is requesting service.
The eDMA hardware automatically clears this flag after the channel begins
execution.
0 The channel is not explicitly started.
1 The channel is explicitly started via a software initiated service request.
Table 8-20. TCDn field descriptions (continued)
Bits /
Word offset
[n:n]
Name Description