NXP Semiconductors MPC5644A, Reference Manual, Page: 801 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 801
24.4.7 Channel configuration and control registers
Each channel has a group of three registers used to control, configure and check status of that channel as
shown in
Table 24-31 . This organization eases individual channel management.
NOTE
1. A bus error is issued on read or write accesses to these registers when ETPU_ECR bit MDIS = 1.
Writes are ineffective on bus error.
2. The SIU_ISEL8 Register is used to multiplex the eTPU[24:29] inputs. When SIU_SEL8 is in its
default state eTPU channels 24–29 will not be connected to their respective output pin, irrespective
of the SIU_PCR[PA] field. See
Section 16.6.22, IMUX Select Register 8 (SIU_ISEL8) .
One contiguous area is used to map all channel registers of each eTPU engine as shown in Table 24-32 .
There are 64 structures defined, one for each available channel in the eTPU System (32 for each engine).
The base address for the structure presented can be calculated by using the following equation:
Table 24-31. Channel registers structure
Channel offset Register name
0x00 ETPU_CxCR – eTPU Channel Configuration Register
0x04 ETPU_CxSCR – eTPU Channel Status/Control Register
0x08 ETPU_CxHSRR – eTPU Channel Host Service Request Register
0x0C RESERVED
Table 24-32. Channel registers map
Offset Registers structure
0x400 eTPU 1 Channel 0 Registers Structure
0x410 eTPU 1 Channel 1 Registers Structure
0x420 eTPU 1 Channel 2 Registers Structure
0x430 .
.
0x5E0 eTPU 1 Channel 30 Registers Structure
0x5F0 eTPU 1 Channel 31 Registers Structure
0x600 RESERVED
0x800 eTPU 2 Channel 0 Registers Structure
0x810 eTPU 2 Channel 1 Registers Structure
0x820 .
.
0x9E0 eTPU 2 Channel 30 Registers Structure
0x9F0 eTPU 2 Channel 31 Registers Structure
0xA00 RESERVED