NXP Semiconductors MPC5644A, Reference Manual, Page: 274 / 1735

Memory Protection Unit (MPU)
MPC5644A Microcontroller Reference Manual, Rev. 6
274 Freescale Semiconductor
(– – – | r – –) = (r – –) permission in this space. Both DMA engines are excluded from this shared
processor data region. The overlapping spaces between RGD3 and RGD4 defines another shared
data space, this one for passing data from CP1 to CP0. For this overlapping space, CP0 has
(r – – | – – –) = (r – –) permission, while CP1 has (r w – | r – –) = (r w –) permission. The
non-overlapped space of RGD4 defines a private data and stack area for CP1 only.
The space defined by RGD5 is a shared data region, accessible by all four bus masters. Finally, the
slave peripheral space mapped onto the peripheral bus is partitioned into two regions: one (RGD6)
containing the MPU’s programming model accessible only to the two processor cores, and the
remaining peripheral region (RGD7) accessible to both processors and the traditional eDMA
master.
This example is intended to show one possible application of the capabilities of the memory
protection unit in a typical system.
WARNING
Program code occupies the end of the MPU region (#0) in which core
instruction accesses are allowed. The address region immediately
afterwards is protected by the MPU (region #1) from instruction fetches by
the core (or any PID=1 access).
If the last instruction in the MPU region #0 space is a branch which the core
takes while the core attempts to fetch instructions via instruction cache line
fill from the MPU region #1 the MPU asserts a bus error (a PID=1
executable access into a region which only allows read/write accesses from
PID=2). The core immediately takes the exception as a 'machine check'.
In this case, modify the 'machine check' exception handler to expect this
behavior.