NXP Semiconductors MPC5644A, Reference Manual, Page: 113 / 1735

Operating Modes and Clocking
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 113
modules, which allows software to disable the non-memory-mapped portions of the modules by setting the
module disable (MDIS
1
) bits in the registers within the modules. The second tier is provided by the
SIU_HLT register, which can be used to halt the clock of both memory-mapped and non-memory-mapped
portions of each module. The third tier is provided by the WAIT instruction of the Power Architecture
instruction set, which controls the clock gating of the CPU itself.
Figure 5-7 illustrates how the MDIS and
halt bits affect the clocks to the modules.
Figure 5-7. MDIS and halt clock gating
5.3.4.5.1 MDIS clock gating
The MDIS bit disables the clock to some or all of the non-memory-mapped registers of the module. The
memory-mapped portion of the modules are clocked by the system clock when they are accessed.
When the NPC module is disabled by MDIS, the MCKO clock is disabled. Furthermore, the NPC can be
configured to disable the MCKO clock when there are no messages pending.
When the EBI module is disabled by MDIS, the CLKOUT clock is disabled. Furthermore, the EBI
automatically disables the CLKOUT clock when there are no transactions on the external (calibration) bus.
The flash memory array can be disabled by writing to a bit in the flash memory map.
The modules that implement the MDIS function are listed in Table 5-2 , along with the registers and bits
that disable each module. The software controlled clocks are enabled when the CPU comes out of reset.
1. For compatibility with legacy devices, the default value of MDIS bit is zero.
MDIS
IP
ipg_stop_ack
ipg_stop
system_clk_enable
SIU
HLT
HLTACK
Memory mapped registers
Non memory mapped
affected by MDIS
system_clk_s
IP Inactive
ips_module_en
system_clk
system_clk
Non memory mapped,
not affected by MDIS
system_clk