NXP Semiconductors MPC5644A, Reference Manual, Page: 1271 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1271
3
EOQF
End of Queue Flag
The EOQF bit indicates that the last entry in a queue has been transmitted when the DSPI in the
master mode. The EOQF bit is set when TX FIFO entry has the EOQ bit set in the command halfword
and the end of the transfer is reached. The EOQF bit remains set until cleared by writing 1 to it. When
the EOQF bit is set, the TXRXS bit is automatically cleared.
0 EOQ is not set in the executed command
1 EOQ bit is set in the executed SPI command
4
TFUF
Transmit FIFO Underflow Flag
The TFUF bit indicates that an underflow condition in the TX FIFO has occurred. The transmit
underflow condition is detected only for DSPI modules operating in slave mode and SPI
configuration. The TFUF bit is set when the TX FIFO of a DSPI operating in SPI slave mode is empty,
and a transfer is initiated by an external SPI master. The TFUF bit remains set until cleared by writing
1 to it.
0 TX FIFO underflow has not occurred
1 TX FIFO underflow has occurred
5 Reserved, should be cleared.
6
TFFF
Transmit FIFO Fill Flag
The TFFF bit provides a method for the DSPI to request more entries to be added to the TX FIFO.
The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be cleared by writing 1 to it or by
acknowledgement from the DMA controller to the TX FIFO full request.
0 TX FIFO is full
1 TX FIFO is not full
7–8 Reserved, should be cleared.
9
DPEF
DSI Parity Error Flag
The DPEF flag indicates that a DSI frame with parity error had been received. The bit remains set
until cleared by writing 1 to it.
0 Parity Error has not occurred
1 Parity Error has occurred
10
SPEF
SPI Parity Error Flag
The SPEF flag indicates that a SPI frame with parity error had been received. The bit remains set
until cleared by writing 1 to it.
0 Parity Error has not occurred
1 Parity Error has occurred
11
DDIF
DSI data received with active bits
The DDIF flag indicates that DSI frame had been received with bits, selected by DSPI_DIMR with
active polarity, defined by DSPI_DPIR. The bit remains set until cleared by writing 1 to it.
0 No DSI data with active bits was received
1 DSI data with active bits was received
12
RFOF
Receive FIFO Overflow Flag
The RFOF bit indicates that an overflow condition in the RX FIFO has occurred. The bit is set when
the RX FIFO and shift register are full and a transfer is initiated. The bit remains set until cleared by
writing 1 to it.
0 RX FIFO overflow has not occurred
1 RX FIFO overflow has occurred
13 Reserved, should be cleared.
Table 30-12. DSPI_SR field description (continued)
Field Description