NXP Semiconductors MPC5644A, Reference Manual, Page: 1138 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
1138 Freescale Semiconductor
25.6.7.2 External multiplexing
The EQADC can use from one to eight external multiplexer chips to expand the number of analog signals
that may be converted. Up to 64 analog channels can be converted through external multiplexer selection.
The externally multiplexed channels are automatically selected by the CHANNEL_NUMBER field of a
Command Message, in the same way done with internally multiplexed channels. The software selects the
external multiplexed mode by setting the ADC0/1_EMUX bit in either ADC0_CR or ADC1_CR
depending on which ADC will perform the conversion.
Table 25-70 shows the channel number
assignments for the multiplexed mode. There are 4 differential pairs, 39 single-ended, and, at most, 64
externally multiplexed channels which can be selected. Only one ADC can have its ADC0/1_EMUX bit
asserted at a time.
INA_ADC0_4 Device Specific Single-ended ADC0 1010_0011 163
INA_ADC0_5 Device Specific Single-ended ADC0 1010_0100 164
INA_ADC0_6 Device Specific Single-ended ADC0 1010_0101 165
INA_ADC0_7 Device Specific Single-ended ADC0 1010_0110 166
INA_ADC0_8 Device Specific Single-ended ADC0 1010_0111 167
Reserved 1010_1000 to
1100_0001
168 to 193
Reserved ADC0 1100_0010 to
1100_0111
194 to 199
INA_ADC1_3 Device Specific Single-ended ADC1 1100_0010 194
INA_ADC1_4 Device Specific Single-ended ADC1 1100_0011 195
INA_ADC1_5 Device Specific Single-ended ADC1 1100_0100 196
INA_ADC1_6 Device Specific Single-ended ADC1 1100_0101 197
INA_ADC1_7 Device Specific Single-ended ADC1 1100_0110 198
INA_ADC1_8 Device Specific Single-ended ADC1 1100_0111 199
Reserved 1100_1000 to
1101_1111
200 to 223
Reserved 1110_0xxx to 1111_1xxx 224 to 255
1
The two on-chip ADCs can access the same analog input pins but simultaneous conversions are not allowed. Also,
when one ADC is performing a differential conversion on a pair of pins, the other ADC must not access either of
these two pins as single-ended channels.
2
Old version has reserved values for channel numbers 8 to 11 when EMUX =1. Therefore, now the behavior is
different because it is converted the signal at AN8 to AN11, respectively.
3
VREF=VRH-VRL.
4
50% x VREF = 50% ref = (VRH / VRL)/2, but this only applies before calibration. After calibration, the 50% reference
point will actually return approximately 20 mV lower than the expected 50% of the difference between the High
Reference Voltage (VRH) and the Low Reference Voltage (VRL). For calibration of the ADC only the 25% and 75%
points should be used as described in
Section 25.7.6, ADC Result Calibration .
Table 25-70. Multiplexed Channel Assignments
1
(continued)
Input Pins ADC
Channel Number in
CHANNEL_NUMBER Field