FlexCAN Module
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
1435
32.5.9.2
Module Disable Mode
This low power mode is entered when the MDIS bit in the MCR Register is asserted. If the module is
disabled during Freeze Mode, the module sends a request to disable the clocks to the CAN Protocol
Interface (CPI) and Message Buffer Management (MBM) sub-modules, sets the LPM_ACK bit and
negates the FRZ_ACK bit. If the module is disabled during transmission or reception, FlexCAN does the
following:
•
Waits to be in either Idle or Bus Off state, or else waits for the third bit of Intermission and then
checks it to be recessive
•
Waits for all internal activities like arbitration, matching, move-in and move-out to finish
•
Ignores its Rx input pin and drives its Tx pin as recessive
•
Shuts down the clocks to the CPI and MBM submodules
•
Sets the NOTRDY and MDISACK bits in MCR
The Bus Interface Unit continues to operate, enabling the CPU to access memory mapped registers, except
the Free Running Timer, the Error Counter Register and the Message Buffers, which cannot be accessed
when the module is in Disable Mode. Exiting from this mode is done by negating MCR[MDIS], which
will resume the clocks and negate MCR[MDISACK].
32.5.9.3
Stop Mode
This is a system low power mode in which all MCU clocks are stopped for maximum power savings. If
FlexCAN receives the global Stop Mode request during Freeze Mode, it sets MCR[MDISACK], negates
MCR[FRZACK] and then sends a Stop Acknowledge signal to the CPU, in order to shut down the clocks
globally. If Stop Mode is requested during transmission or reception, FlexCAN does the following:
•
Waits to be in either Idle or Bus Off state, or else waits for the third bit of Intermission and checks
it to be recessive
•
Waits for all internal activities like arbitration, matching, move-in and move-out to finish
•
Ignores its Rx input pin and drives its Tx pin as recessive
•
Sets the NOTRDY and MDISACK bits in MCR
•
Sends a Stop Acknowledge signal to the CPU, so that it can shut down the clocks globally
Exiting Stop Mode is done in one of the following ways:
•
CPU resuming the clocks and removing the Stop Mode request
•
CPU resuming the clocks and Stop Mode request as a result of the Self Wake mechanism
In the Self Wake mechanism, if MCR[SLF_WAK] was set at the time FlexCAN entered Stop Mode, then
upon detection of a recessive to dominant transition on the CAN bus, FlexCAN sets ESR[WAKINT] and,
if enabled by MCR[WAK_MSK], generates a Wake Up interrupt to the CPU. Upon receiving the interrupt,
the CPU should resume the clocks and remove the Stop Mode request. FlexCAN will then wait for 11
consecutive recessive bits to synchronize to the CAN bus. As a consequence, it will not receive the frame
that woke it up.
details the effect of MCR[SLF_WAK] and MCR[WAK_MSK] upon wake-up
from Stop Mode. Note that wake-up from Stop Mode only works when both bits are asserted.
Summary of Contents for MPC5644A
Page 2: ...MPC5644A Microcontroller Reference Manual Rev 6 2 Freescale Semiconductor...
Page 24: ...MPC5644A Microcontroller Reference Manual Rev 6 24 Freescale Semiconductor...
Page 26: ...MPC5644A Microcontroller Reference Manual Rev 6 26 Freescale Semiconductor...
Page 52: ...Introduction MPC5644A Microcontroller Reference Manual Rev 6 52 Freescale Semiconductor...
Page 56: ...Memory Map MPC5644A Microcontroller Reference Manual Rev 6 56 Freescale Semiconductor...
Page 1228: ...Decimation Filter MPC5644A Microcontroller Reference Manual Rev 6 1228 Freescale Semiconductor...
Page 1440: ...FlexCAN Module MPC5644A Microcontroller Reference Manual Rev 6 1440 Freescale Semiconductor...