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Reaction Module (REACM)
MPC5644A Microcontroller Reference Manual, Rev. 6
690
Freescale Semiconductor
5. Hold-off timer bank data (see
Section 23.3.11, REACM Hold-off Timer Bank Registers
(REACM_HOTBK)
)
6. Timer router data (see
Section 23.3.9, REACM Channel n Router Register (REACM_CHRRn)
)
7. ADC router data (see
Section 23.3.4, REACM Threshold Router Register (REACM_THRR)
)
The last action to perform is to
enable
the channel, after which the channel is able to respond to timer
signals and ADC data, thus able to perform modulation on the output pins. It is recommended to keep the
timer signals inactive until all data to all reaction channel modules are programmed and all channels have
been put in the
enabled
mode.
23.1.2.2
Low power mode
Coming out of reset all channels are in the disabled state. The channel may also be in low power mode
depending on a parameter that configures the initial state of the MDIS in the REACM module
configuration register (REACM_MCR) (see
). If REACM_MCR[MDIS] = 1 the module clock
may be disabled allowing for a low power state. The low power mode is controlled either by
REACM_MCR[MDIS] or by a global stop signal. There is no explicit clock gating implemented in
hardware within the reaction module.
NOTE
Low power mode must be entered only when all channels are disabled by
REACM_CHCRn[CHEN] = 00.
23.1.2.3
Channel modes
After a channel is in
enabled
mode that channel is also said to be in the
normal
mode of operation, which
means it responds to timer signals from the timer inputs connected to the reaction module and also to ADC
results received from the on-chip ADC module. Channel outputs are controlled in accordance with those
inputs in order to perform an output modulation process. When performing a modulation the reaction
channel is said to be in the
active state
. The modes a reaction channel can be in and the ability to execute
a modulation related to the modes are:
•
Disabled: The channel cannot execute modulation.
•
Enabled: The channel is able to execute a modulation. It may be in the
Active
or
Inactive
state.
— Inactive state: The channel is not executing a modulation.
— Active state: The channel is executing a modulation.
23.1.2.4
Debug mode
The Reaction Module Debug operation is defined by bits FRZ and FREN in the REACM module
configuration register (REACM_MCR) (see
). In debug mode all timers are halted, including
the timers in the Shared Time Bank and Hold-off Timers.
The module can enter debug mode either by software control or by the hardware debug input signal
controlled by the chip logic. In both cases the reaction module only enters debug mode if enabled by bit
REACM_MCR[FREN]:
•
If the FREN bit and the FRZ bit are both is asserted the module enters debug mode.
Summary of Contents for MPC5644A
Page 2: ...MPC5644A Microcontroller Reference Manual Rev 6 2 Freescale Semiconductor...
Page 24: ...MPC5644A Microcontroller Reference Manual Rev 6 24 Freescale Semiconductor...
Page 26: ...MPC5644A Microcontroller Reference Manual Rev 6 26 Freescale Semiconductor...
Page 52: ...Introduction MPC5644A Microcontroller Reference Manual Rev 6 52 Freescale Semiconductor...
Page 56: ...Memory Map MPC5644A Microcontroller Reference Manual Rev 6 56 Freescale Semiconductor...
Page 1228: ...Decimation Filter MPC5644A Microcontroller Reference Manual Rev 6 1228 Freescale Semiconductor...
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