NXP Semiconductors MPC5644A, Reference Manual, Page: 1307 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1307
Figure 30-39. DSPI Transfer Timing Diagram (MTFE = 0, CPHA = 1, FMSZ = 8)
The master initiates the transfer by asserting the PCS signal to the slave. After the
t
CSC
delay has elapsed,
the master generates the first SCK edge and at the same time places valid data on the master SOUT pin.
The slave responds to the first SCK edge by placing its first data bit on its slave SOUT pin.
At the second edge of the SCK the master and slave sample their SIN pins. For the rest of the frame the
master and the slave change the data on their SOUT pins on the odd-numbered clock edges and sample
their SIN pins on the even-numbered clock edges. After the last clock edge occurs a delay of
t
ASC
is inserted
before the master negates the PCS signal. A delay of t
DT
is inserted before a new frame transfer can be
initiated by the master.
30.9.6.3 Modified SPI/DSI transfer format (MTFE = 1, CPHA = 0)
In this Modified Transfer Format both the master and the slave sample later in the SCK period than in
Classic SPI mode to allow tolerate more delays in device pads and board traces. These delays become a
more significant fraction of the SCK period as the SCK period decreases with increasing baud rates.
The master and the slave place data on the SOUT pins at the assertion of the PCS signal. After the PCS to
SCK delay has elapsed the first SCK edge is generated. The slave samples the master SOUT signal on
every odd numbered SCK edge. The DSPI in the slave mode when the MTFE bit is set also places new
data on the slave SOUT on every odd numbered clock edge. Regular external slave, configured with
CPHA = 0 format drives its SOUT output at every even numbered SCK clock edge.
t
CSC
t
DT
SCK
SCK
MSB first (LSBFE = 0):
LSB first (LSBFE = 1): MSB
LSB
LSB
MSB
Bit 5
Bit 2 Bit 6
Bit 1 Bit 4
Bit 3 Bit 3
Bit 4 Bit 2
Bit 5 Bit 1
Bit 6
t
CSC
= PCS to SCK delay
t
DT
= Delay after Transfer (minimum CS negation time)
(CPOL = 0)
(CPOL = 1)
t
ASC
Master SOUT/
Master SIN/
Slave SIN
Slave SOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PCSx/SS
Master and Slave
Sample
t
ASC
= After SCK delay