NXP Semiconductors MPC5644A, Reference Manual, Page: 1638 / 1735

Power Management Controller (PMC)
MPC5644A Microcontroller Reference Manual, Rev. 6
1638 Freescale Semiconductor
35.2.1.1 VDDREG
Quiet 5 V supply for the voltage regulator and LVI block. It must have an external decoupling capacitor
of the order of 4.7 µF – 20 µF. Regulators and LVI can be turned off by grounding VDDREG. In this case
external regulation and low voltage control must be supplied.
35.2.1.2 VDDEH1
Power supply input (5 V or 3.3 V nominal), taken from one of the pad ring I/O segment which is near the
voltage regulator.
35.2.1.3 VRC33
When the internal 3.3 V voltage regulator is enabled, this pin must be connected to an external bypass
capacitor of 600 nF – 2 µF with low ESR (max 50 m

). If the voltage regulator is not powered or the
regulator is disabled (pin VDDREG to ground or shutdown bit PMC_SR[V33DIS] set to ‘1’), this pin must
be connected to an external 3.3 V supply.
35.2.1.4 VDD
This is the 1.2 V supply coming from the emitter of an external NPN ballast transistor, whose base current
is supplied by VRCCTL. If the internal voltage regulator controller is not powered (pin VDDREG tied to
ground) or the external ballast transistor is not present, the VDD pin must be connected to an external 1.2 V
power supply.
For maximum transient performance, the recommended bypass capacitor for each pin that supplies the
digital core is 2.2 µF – 6 µF with very low ESR (max 50 m

). A ceramic capacitor is also desirable, with
100 nF capacitance. Moreover, a 1 µF to 2 µF cap might be connected to the base of the external bipolar.
35.2.1.5 VRCCTL
1.2 V regulator output that drives the base of the external NPN transistor.
35.3 Memory map/register definition
Table 35-2 shows the PMC memory map. The PMC memory map has three registers for configuring,
monitoring, and trimming the LVI monitors.
NOTE
The PMC base address (PMC_BASE) is 0xC3FB_C000. Register addresses
in this chapter are given as offsets to PMC_BASE.