Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
1037
4
CFUFx
CFIFO Underflow Flag x
CFUFx indicates an underflow event on CFIFOx. CFUFx
is set when CFIFOx is in
TRIGGERED state and it becomes empty. No commands will be transferred from an
underflowing CFIFO, nor will command transfers from lower priority CFIFOs be blocked.
When CFUIEx in
Section 25.5.2.8, EQADC Interrupt and DMA Control Registers
, and CFUFx are both asserted, the EQADC generates an interrupt request.
Apart from generating an independent interrupt request for a CFIFOx underflow event, the
EQADC also provides a combined interrupt at which the Result FIFO Overflow Interrupt, the
Command FIFO Underflow Interrupt, and the Command FIFO Trigger Overrun Interrupt
requests of ALL CFIFOs are ORed. When RFOIEx, CFUIEx, and TORIEx are all asserted,
this combined interrupt request is asserted whenever one of the following 18 flags becomes
asserted: RFOFx, CFUFx, and TORFx (assuming that all interrupts are enabled). See
Section 25.6.8, EQADC DMA/Interrupt request
, for details.
Write “1” to clear CFUFx. Writing a “0” has no effect.
1 A CFIFO underflow event occurred.
0 No CFIFO underflow event occurred.
5
SSSx
CFIFO Single-Scan Status Bit x
An asserted SSSx bit enables the detection of trigger events for CFIFOs programmed into
single-scan level- or edge-trigger mode, and works as trigger for CFIFOs programmed into
single-scan software-trigger mode. Refer to
Section 25.6.4.6.2, Single-Scan Mode
, for
further details. The SSSx bit is set by writing a “1” to the SSEx bit in
EQADC CFIFO Control Registers (EQADC_CFCR)
. The EQADC clears the SSSx bit when
a command with an asserted EOQ bit is transferred from a CFIFO in single-scan mode,
when a CFIFO is in single-scan level-trigger mode and its status changes from TRIGGERED
due to the detection of a closed gate, or when the value of the CFIFO operation mode
(MODEx) in
Section 25.5.2.7, EQADC CFIFO Control Registers (EQADC_CFCR)
changed to disabled. Writing to SSSx has no effect. SSSx has no effect in continuous-scan
or in disabled mode.
1 CFIFO in single-scan level- or edge-trigger mode will detect a trigger event, or CFIFO in
single-scan software-trigger mode is triggered.
0 CFIFO in single-scan level- or edge-trigger mode will ignore trigger events, or CFIFO in
single-scan software-trigger mode is not triggered.
6
CFFFx
CFIFO Fill Flag x
CFFFx
is set when the CFIFOx is not full. When CFFE
x
Interrupt and DMA Control Registers (EQADC_IDCR)
, and CFFFx are both asserted, an
interrupt or a DMA request will be generated depending on the status of the CFFSx bit. When
CFFSx is negated (interrupt requests selected), software clears CFFFx by writing a “1” to it.
Writing a “0” has no effect. When CFFSx is asserted (DMA requests selected), CFFFx is
automatically cleared by the EQADC when the CFIFO becomes full.
1 CFIFOx is not full.
0 CFIFOx is full.
Note:
Writing “1” to CFFFx when CFFSx is asserted (DMA requests selected) is not allowed.
Note:
When generation of interrupt requests is selected (CFFSx=0), CFFFx must only be
cleared in the ISR after the CFIFOx push register is accessed.
Table 25-15.
EQADC
FIFO and Interrupt Status Register x (
EQADC
_FISRx) field description (continued)
Field
Description
Summary of Contents for MPC5644A
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