Interrupt Controller (INTC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
351
NOTE
The INTC_IACKR must not be read speculatively while in software vector
mode. Therefore, for future compatibility, the TLB entry covering the
INTC_IACKR must be configured to be guarded.
In software vector mode, the INTC_IACKR must be read before setting
MSR[EE]. No synchronization instruction is needed after reading the
INTC_IACKR and before setting MSR[EE].
However, the time for the processor to recognize the assertion or negation
of the external input to it is not defined by the book E architecture and can
be greater than 0. Therefore, insert instructions between the reading of the
INTC_IACKR and the setting of MSR[EE] that consumes at least two
processor clock cycles. This length of time allows the interrupt request
negation to propagate through the processor before MSR[EE] is set.
Figure 15-9. INTC Interrupt Acknowledge Register (INTC_IACKR)—INTC_MCR[VTES] = 0
Figure 15-10. INTC Interrupt Acknowledge Register (INTC_IACKR)—INTC_MCR[VTES] = 1
Address: Base + 0x0010 (INTC_IACKR)
Access: R/W
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
VTBA (most significant 16 bits)
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
VTBA (least significant 5 bits)
INTVEC
1
1
When the VTES bit in the INTC Module Configuration Register (INTC_MCR)
is asserted, INTVEC is shifted to the
left one bit. Bit 29 is read as a ‘0’. VTBA is narrowed to 20 bits in width.
0
0
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Address: Base + 0x0010 (INTC_IACKR)
Access: R/W
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
VTBA (most significant 16 bits)
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
VTBA (least significant 4
bits)
INTVEC
1
1
When the VTES bit in the INTC Module Configuration Register (INTC_MCR)
is asserted, INTVEC is shifted to the
left one bit. Bit 29 is read as a ‘0’. VTBA1 is narrowed to 20 bits in width.
0
0
0
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Summary of Contents for MPC5644A
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