NXP Semiconductors MPC5644A, Reference Manual, Page: 1376 / 1735

Enhanced Serial Communication Interface (ESCI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1376 Freescale Semiconductor
If the receiver has not detected an overrun and has detected a framing error as described in
Section 31.4.5.3.13, Bit sampling ” the FE flag is set.
If the receiver has not detected an overrun and has detected a parity error as described in
Section 31.4.5.3.18, Parity checking ” the PF flag is set.
31.4.5.5 Multiprocessor communication
The multiprocessor communication allows one processor to send blocks of frames to other processors on
the same serial link. To avoid the received data interrupt for frames not intended for the processor, the eSCI
receiver can be put into the Wake-up state. If the receiver is in the Wake-up state, the eSCI will still load
the received data into the
SCI data register (eSCI_DR) , but will not set the RDRF flag and consequently
not request the RDRF interrupt.
The receiver leaves the Wake-up state and clears the RWU bit in the Control register 1 (eSCI_CR1) when
the wake-up pattern configured by WAKE bit in Control register 1 (eSCI_CR1) is received. The eSCI
module supports two types of wake-up patterns, the idle-line wakup pattern and the address-mark wake-up
pattern.
31.4.5.5.1 Idle-Line wake up
The idle-line wake-up mode is selected when the WAKE bit in Control register 1 (eSCI_CR1) is 0. In this
mode, the receiver leaves the wake-up state, when an idle character is detected as described in
Section 31.4.5.3.8, Idle character detection ”. The next received frame is the address frame that contains
address information which can be evaluated by the application. If the application decides not to receive the
frame block, it can set the RWU bit in the
Control register 1 (eSCI_CR1) and return the receiver to the
wake-up state.
Figure 31-34. Idle-Line Wake Up
31.4.5.5.2 Address-Mark wake up
The address-mark wake-up mode is selected when the WAKE bit in Control register 1 (eSCI_CR1) is 1.
If the WAKE bit is set, the address bit is added to the frame format. In this mode, the receiver leaves the
wake-up state, when a data frame with the address bit value of 1 was received. This frame is the address
frame and contains address information which can be evaluated by the application. If the application
decides not to receive the frame block, it can set the RWU bit in the
Control register 1 (eSCI_CR1) and
return the receiver to the wake-up state. All data frames that belong to the frame block must have the
address bit cleared.
Figure 31-35. Address-Mark Wake Up
Frame Block Frame Block Idle Character
Receiver Wake Up
Address Frame