NXP Semiconductors MPC5644A, Reference Manual, Page: 725 / 1735

Reaction Module (REACM)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 725
interactively calibrate the modulation levels or capture on-the-fly levels from the external application
board for debug purposes. The REACM_THRR is used for that purpose. See
Figure 23-6 for more details
about the register architecture. Figure 23-25 describes the main connections between the ADC interface
and threshold bank submodules.
The routing of received ADC results to be stored in the threshold bank is independent from the routing of
the same result to the reaction channels (see
Figure 23-11 ). Thus the same ADC result can be used in a
comparison and stored in the threshold bank.
Figure 23-25. ADC interface and threshold bank interconnections
23.4.7 Prescalers
The prescalers provide internal system clock divided signals to be used by internal timers. The reaction
module contains two prescalers: a 12-bit prescaler HPRE[11:0] and an 8-bit prescaler TPRE[7:0]. Both are
defined in the REACM Timer Configuration Register (REACM_TCR) (see
Figure 23-5 for details).
Prescaler HPRE[11:0] is dedicated to the Hold-off timers within the reaction channels. Prescaler
TPRE[7:0] is used by the Shared Timer Bank counters. The HPRE[11:0] and TPRE[7:0] prescalers are
enabled by HPREN and TPREN bits, respectively, in the REACM module configuration register
(REACM_MCR) (see
Figure 23-4 ). Note that prescalers operate in a similar way regarding their
activation. Once the prescaler is enabled by HPREN or TPREN bits in the REACM_MCR, it starts a new
count sequence meaning that it is put in reset state and will generate the first prescaler tick after it reaches
the programmed value defined by the HPRE or TPRE fields.
23.4.8 Banked mode support
Banked Mode is a reaction module hardware configuration which allows the sharing of reaction channel
output pins at the device I/O level. The banked mode architecture allows the stacking of up to four reaction
channels.
Figure 23-26 shows the connection between two adjacent channels, CH0 and CH1. The
REACM_CHCRn BSB bits are used to control the configuration of channel output logic. Thus if BSB[0]
adc_data[15:0]
Comp
Bank
Reg
Write
Logic
CPU
ADC
Interface
on-chip
ADC
Threshold
Bank
THRR
write to threshold bank
Threshold Router register
to Comparator
wr_en