NXP Semiconductors MPC5644A, Reference Manual, Page: 699 / 1735

Reaction Module (REACM)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 699
23.3.3 REACM Timer Configuration Register (REACM_TCR)
The REACM Timer Configuration Register (REACM_TCR) contains the prescaler settings to configure
the operation of the Reaction Module Holdoff Timer and Shared Timers. It is recommended to change the
value of the prescalers either when the prescalers are disabled by its control enable bits HPREN and
TPREN in the REACM_MCR or when the counters are not being used by any channel. Note that the
prescalers are completely independent, thus modifying HPRE does not affect TPRE and modifying TPRE
does not affect HPRE.
Figure 23-5. REACM Timer Configuration Register (REACM_TCR)
6
HPREN
Hold-off Prescaler Enable
The HPREN bit enables the Hold-off Prescaler in the Reaction Module.
0 Prescaler Disabled
1 Prescaler Enabled
7
GIEN
Global Interrupt Enable
The GIEN bit enables the assertion of the interrupt request to the CPU when any of the channel flags or
the OVR flag are set. The channel error flag bits are: MAXL, OCDF, SCDF and TAER. Note that for the
interrupt to be asserted these flag bits need also to be enabled by the corresponding enable bit defined
in
Section 23.3.7, REACM Channel n Configuration Register (REACM_CHCRn) .
0 Interrupt disabled
1 Interrupt enabled
Note: The GIEN bit only affects the general interrupt signal, and not the individual channel interrupts.
GIEN=0 does not inhibit the channel interrupts.
8
OVREN
Overrun Detection Interrupt Enable
The OVREN enables the OVR flag, when set, to generate a global interrupt request for the CPU.
0 Interrupt disabled
1 Interrupt enabled
9–31 Reserved, should be cleared.
Address: REACM_BASE (0xC3FC_7000) + 0x0004 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
HPRE[11:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0
TPRE[7:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 23-4. REACM_MCR field descriptions (continued)
Field Description