NXP Semiconductors MPC5644A, Reference Manual, Page: 680 / 1735

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5644A Microcontroller Reference Manual, Rev. 6
680 Freescale Semiconductor
Figure 22-35 describes the operation of the OPWMB mode regarding A1 and B1 matches and the
transition of the channel output pin. In this example EDPOL is set to zero.
Figure 22-35. OPWMB mode matches and flags
Note that the output pin transitions are based on the negedges of the A1 and B1 match signals.
Figure 22-35 shows in cycle n+1 the value of A1 register being set to zero. In this case the match posedge
is used instead of the negedge to transition the output flip-flop.
Figure 22-36 describes the channel operation for 0% duty cycle. Note that the A1 match posedge signal
occurs at the same time as the B1 = 0x8 negedge signal. In this case A1 match has precedence over B1
match, causing the output pin to remain at EDPOL bit value, thus generating a 0% duty cycle signal.
1
4
match A1 negedge detection
6
A1 value 0x000004
A1 match
A1 match negedge detection
output pin
EDPOL = 0
TIME
match B1 negedge detection
B1 match
B1 match negedge detection
B1 value
0x000006
clock
prescaler
A2 value
0x000000
write to A2
0x000000
A1 match posedge detection
match A1 posedge detection
1
cycle n
cycle n+1
8
6
FLAG set event
Selected
counter bus
FLAG pin/register