NXP Semiconductors MPC5644A, Reference Manual, Page: 708 / 1735

Reaction Module (REACM)
MPC5644A Microcontroller Reference Manual, Rev. 6
708 Freescale Semiconductor
23.3.9 REACM Channel n Router Register (REACM_CHRRn)
The REACM Channel n Router Register (REACM_CHRRn) controls the channel interconnection to
external timers, such as eTPU and eMIOS and ADC result data. The channels have access to any 16 timer
inputs and any ADC sample tag from 0 to 15. Note that this architecture allows several reaction channels
to point to the same timer channel or to the same ADC result.
21
SCDFC
Short Circuit Detection Flag clear
The SCDFC bit clears the SCDF flag if write ‘1’. This bit is self negated thus read always as ‘0’.
If a set event occurs at the same time a flag clear is done, the set event has precedence over
the clear thus the flag remains set.
1 Clears SCDF
0 No action
22
TAERC
TAER Clear bit
The TAERC bit clears the TAER bit if write ‘1’. This bit is self-negated thus reads always as ‘0’.
If a set event occurs at the same time a flag clear is done, the set event has precedence over
the clear thus the flag remains set.
1 Clears TAER
0 No action
23
SQERC
Modulation Word Sequence Error Flag clear
The SQERC bit clears the SQER flag in the Channel Status register.
1 SQER flag is cleared
0 SQER flag is not cleared
24
RAERC
Resource Allocation Error Flag clear
The RAERC bit clears the RAER flag in the Channel Status register.
1 RAER flag is cleared
0 RAER flag is not cleared
25 Reserved, should be cleared.
26–31
MODULATION_
POINTER[5:0]
Modulation bank address generated by the channel
The MODULATION_POINTER[5:0] gives to the software the information of the current address
being generated by the channel to access the Modulation Word. Note that the address
increments from a base address stored in the channel, MODULATION_ADDR[5:0]. This register
is not buffered thus represents the current address being generated.
Table 23-11. REACM_CHSRn field descriptions (continued)
Field Description