NXP Semiconductors MPC5644A, Reference Manual, Page: 1602 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
1602 Freescale Semiconductor
The behavior of the CC after the occurrence of a system bus failure is defined by the SBFF bit in the
Module Configuration Register (FR_MCR) .
33.6.19.1.1 System bus illegal address access
If the system bus detects an CC access to an illegal address, the CC receives a notification from the system
bus about this event and sets the ILSA_EF flag in the
CHI Error Flag Register (FR_CHIERFR) .
33.6.19.1.2 System bus access timeout
A system bus access timeout is detected if an access to the flexray memory area is not finished in time.
The timeout value is derived from the SYMATOR[TIMEOUT] setting (see
Section 33.7.1.1, Configure
System Memory Access Time-Out Register (FR_SYMATOR) ”
If a system bus access timeout is detected, the CC sets the SBCF_EF flag in the CHI Error Flag Register
(FR_CHIERFR) .
33.6.19.2 System bus access failure response
This section describes the two types of behavior of the CC after the occurrence of a system bus access
failure. The actual behavior is defined by the SBFF bit in the
Module Configuration Register (FR_MCR) .
33.6.19.2.1 Continue after system bus access failure
If the SBFF bit in the Module Configuration Register (FR_MCR) is 0, the CC will continue its operation
after the occurrence of the system bus access failure, but will not generate any system bus accesses until
the start of the next communication cycle.Since no data are read from or written to the flexray memory
area, no messages are received or transmitted. Consequently, none of the individual message buffers or
receive FIFOs will be updated until the next communication cycle starts.
If a frame is under transmission when the system bus failure occurs, a correct frame is generated with the
remaining header and frame data are replaced by all zeros. Depending on the point in time this can affect
the PPI bit, the Header CRC, the Payload Length in case of an dynamic slot, and the payload data. Starting
from the next slot in the current cycle, no frames will be transmitted and received, except for the key slot,
where a sync or startup null-frame is transmitted, if the key slot is assigned.
If a frame is received when the system bus failure occurs, the reception is aborted and the related receive
message buffer is not updated.
Normal operation is resumed after the start of next communication cycle.
33.6.19.2.2 Freeze after system bus access failure
If the SBFF bit in the Module Configuration Register (FR_MCR) is set to 1, the CC will go into the freeze
mode immediately after the occurrence of one of the system bus access failures.
33.6.20 Interrupt support
The CC provides 172 individual interrupt sources and five combined interrupt sources.