NXP Semiconductors MPC5644A, Reference Manual, Page: 1616 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
1616 Freescale Semiconductor
Application Write Access (I_ADDR = 0x70):
1. FR_PEDRAR:= 0x30E0; // INST = 0x3; ADDR = 0x70
2. wait until FR_PEDRAR[DAD] == 1; // wait for end of PE DRAM access
3. val = FR_PEDRDR[DATA]; // get read back PE DRAM data
NOTE
The write access to the PE DRAM triggers a read from PE DRAM in the
next cycle, which triggers the detection of the distorted data.
33.7 Application information
33.7.1 Module configuration
This section describes essential parts of the module configuration.
33.7.1.1 Configure System Memory Access Time-Out Register (FR_SYMATOR)
To ensure reliable operation of the CC, the application has to ensure that the TIMEOUT value in System
Memory Access Time-Out Register (FR_SYMATOR) and the CHI clock frequency f
CHI
in MHz fulfill
Equation 33-29
1
.
Eqn. 33-29
If the SYMATOR[TIMEOUT] value and f
CHI
violates Equation 33-29 , the behavior of the CC becomes
unreliable and undefined. It may happen that frames are not transmitted at all, including key slot frames.
For a given SYMATOR[TIMEOUT] value f
CHI
can be increased without causing unreliable operation of
the CC. The same holds for reducing the SYMATOR[TIMEOUT] value for a given f
CHI
.
Some examples for maximum values of the SYMATOR[TIMEOUT] for a minimum CHI frequency are
given in
Table 33-135
.
1. See Section 33.3, Controller host interface clocking ” for all constraints of minimum CHI clock frequency.
Table 33-135. Maximum SYMATOR[TIMEOUT] examples
f
CHI
SYMATOR[TIMEOUT] f
CHI
SYMATOR[TIMEOUT]

18 MHz 0

100 MHz

37

23 MHz

2

120 MHz

46

27 MHz

4

140 MHz

55

32 MHz

6

160 MHz

64

60 MHz

19

180 MHz

73

80 MHz

28

200 MHz

82
0 SYMATOR[TIMEOUT] 0.45 f
CHI

8 –
 