NXP Semiconductors MPC5644A, Reference Manual, Page: 1299 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1299
Figure 30-33. DSPI parallel chaining example
In the parallel chaining example, the SOUT and SIN of the three DSPIs connect to separate external SPI
devices. All internal and external SPI blocks share PCS and SCK signals. DSPI_B controls and initiates
all transfers, but the DSPI slaves each have a trigger output signal MTRIG that indicates to DSPI_B that
a trigger condition has occurred in the DSPI slaves. When the slave DSPI has a change in data to be
serialized, it asserts the MTRIG signal that propagates to DSPI_B which initiates the transfer.
30.9.3.7 Serial chaining
Serial chaining allows SPI operation with an external device that has more bits than one DSPI module. In
a serial chain, one DSPI module operates as a master, the other DSPI modules operate as slaves.
The data output (SOUT) of the master is connected to the data input (SIN) of the slave. The SOUT of a
slave is connected to the SIN of subsequent slaves until the last block in the chain, where the SOUT is
connected to an external pin, which connects to the input of an external SPI device. The slave DSPI and
external SPI device use the master peripheral chip select (PCS) and clock (SCK).
The Trigger input of the master allows a slave DSPI to trigger a transfer when a data change occurs in the
slave DSPI and the slave DSPI is operating in Change in Data mode. The Trigger input of the master is
connected to MTRIG output of the slave.
The concatenated frames can be from 8 to 64 bits long. Figure 30-34 shows an example of how the blocks
can be connected in the MPC5644A.
SOUT
SOUT
SIN
SIN
PCS[x]
SS
SCK
SCK
DSPI_B Master
DSPI_C Slave
SS
SCK
SIN
SOUT
DEVICE
SIN
SCK SS
SOUT
MTRIG
HT
SPI Slave Device SPI Slave Device
SOUT
SIN
SS
SCK
DSPI_D Slave
SIN
SCK SS
SOUT
MTRIG
SPI Slave Device
HT
SO
UT_C
SI
N_C
SI
N_B
PCS_B[
0]
SCK
_
B
SOUT_
B
SO
UT
_
D
SIN_D