NXP Semiconductors MPC5644A, Reference Manual, Page: 921 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 921
Flags N and Z on shift are updated according to the result after shift. Flag V with shift is updated according
to the ADD operation only, the same way as without shift.
24.5.8.2.3 ADC operation
ADC operation is selected by the ALUOP field. CIN field is ignored when this operation is selected.
Table 24-65 describes how BINV change ADC operation behavior.
Flags behave exactly the same way as for ADD operation without shift/rotate.
24.5.8.2.4 Bitwise Operations
Bitwise AND, OR and XOR are selected by ALUOP field. On these operations CIN field is ignored and
BINV field inverts (bitwise NOT) BS. C and V Flags are never updated on these operations.
Table 24-66
Describes AND, OR and XOR bitwise operations.
0 8 bits rotate right !adder carry from bit 7 to bit 8
0 16 bits rotate right !adder carry from bit 15 to bit 16
0 24 bits rotate right !alu_adder_output[24]
Except on max-constant generation (see Section , Max constant generation
with T4BBS = 111 )
1
BINV has no effect on carry-out when used to code max constant (see Section , Max constant generation with
T4BBS = 111 ).
Table 24-65. Types of ADC operations
BINV CIN Operation
1 x AS + BS + C flag
0 x AS - BS - C flag
Table 24-66. Types of Bitwise Operations
ALUOP BINV Operation
10000 1 AS | BS
10000 0 AS | (~BS)
10001 1 AS ^ BS
10001 0 AS ^ (~BS)
10010 1 AS & BS
10010 0 AS & (~BS)
Table 24-64. Carry flag update on ADD operation (continued)
BINV
1
Operation size Shift/rotate Value