NXP Semiconductors MPC5644A, Reference Manual, Page: 1619 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1619
For a shutdown the application shall perform the following tasks:
1. Disable all enabled message buffers.
a) Repeatedly write ‘1’ to FR_MBCCSRn[EDT] until FR_MBCCSRn[EDS] == 0.
2. Stop Protocol Engine.
a) Issue HALT command via Protocol Operation Control Register (FR_POCR)
b) Wait for POC:halt in Protocol Status Register 0 (FR_PSR0)
33.7.6 Number of usable message buffers
This section describes the required minimum CHI clock frequency for a specified number of utilized
message buffers configured in the
Message Buffer Segment Size and Utilization Register
(FR_MBSSUTR) , a configured minislot length gdMinislot , and a configured nominal macrotick length
gdMacrotick
1
.
Additional constraints for the minimum CHI clock frequency are given in Section 33.3, Controller host
interface clocking ”.
The CC uses a sequential search algorithm to determine the individual message buffer assigned or
subscribed to the next slot. This search is started at the start of slot and must be finished before the start of
the next slot.
The shortest FlexRay slot is an corrected empty dynamic slot. An corrected empty dynamic slot is a
minislot and consists of
gdMinislot corrected macroticks with a duration of gdMacrotick . The minimum
duration of an corrected macrotick is gdMacrotick
min
= 39 µT. This results in a minimum length of an
correct slot
Eqn. 33-30
The message buffer search engine runs on the CHI clock and evaluates one individual message buffer per
CHI clock cycle. For internal status update operations and to account for clock domain crossing jitter, an
additional amount of 10 CHI clock cycles is required to ensure correct search engine operation.
For a given number of utilized message buffers FR_MBSSUTR[LAST_MB_UTIL] + 1 and for a given
CHI clock frequency f
chi
, this results in a search duration of
Eqn. 33-31
The message buffer search must be finished within one slot which requires that Equation 33-32 must be
fulfilled:
Eqn. 33-32
This results in the formula given in Equation 33-33 which determines the required minimum CHI
frequency for a given number of message buffers that are utilized.
Eqn. 33-33
1. See Section 33.3, Controller host interface clocking ” for all constraints of minimum CHI clock frequency.

slotmin
39 pdMicrotick gdMinislot
 
=

search
1
f
chi
-------- FR_MBSSUTR[LAST_M10
  
=

search

slotmin

f
chi
FR_MBSSUTR[LAST_M10
 
39 pdMicrotick gdMinislot
 
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