NXP Semiconductors MPC5644A, Reference Manual, Page: 1487 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1487
33.5.2.31 Combined Interrupt Flag Register (FR_CIFR)
This register provides five combined interrupt flags and a copy of three individual interrupt flags. The
combined interrupt flags are the result of a binary OR of the values of other interrupt flags regardless of
the state of the interrupt enable bits. The generation scheme for the combined interrupt flags is depicted in
Figure 33-162 . The individual interrupt flags WUPIF, FAFBIF, and FAFAIF are copies of corresponding
flags in the Global Interrupt Flag and Enable Register (FR_GIFER) and are provided here to simplify the
application interrupt flag check. To clear the individual interrupt flags, the application must use the Global
Interrupt Flag and Enable Register (FR_GIFER) .
NOTE
The meanings of the combined status bits MIF, PRIF, CHIF, RBIF, and
TBIF are different from those mentioned in the
Global Interrupt Flag and
Enable Register (FR_GIFER) .
Base + 0x003C
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 0 0 0 0 0 0
MI
F
PRIF
CHIF
WUPI
F
FA
F
B
IF
FA
FA
IF
RBIF TBI
F
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 33-31. Combined Interrupt Flag Register (FR_CIFR)
Table 33-36. FR_CIFR field description
Field Description
MIF Module Interrupt Flag — This flag is set if there is at least one interrupt source that has its interrupt
flag asserted.
0 No interrupt source has its interrupt flag asserted
1 At least one interrupt source has its interrupt flag asserted
PRIF Protocol Interrupt Flag — This flag is set if at least one of the individual protocol interrupt flags in the
Protocol Interrupt Flag Register 0 (FR_PIFR0) or Protocol Interrupt Flag Register 1 (FR_PIFR1) is
equal to 1.
0 All individual protocol interrupt flags are equal to 0
1 At least one of the individual protocol interrupt flags is equal to 1
CHIF CHI Interrupt Flag — This flag is set if at least one of the individual CHI error flags in the CHI Error
Flag Register (FR_CHIERFR) is equal to 1.
0 All CHI error flags are equal to 0
1 At least one CHI error flag is equal to 1
WUPIF Wakeup Interrupt Flag — Provides the same value as FR_GIFER[WUPIF]
FAFBIF Receive FIFO Channel B Almost Full Interrupt Flag — Provides the same value as
FR_GIFER[FAFBIF]
FAFAIF Receive FIFO Channel A Almost Full Interrupt Flag — Provides the same value as
FR_GIFER[FAFAIF]