NXP Semiconductors MPC5644A, Reference Manual, Page: 1663 / 1735

JTAG Controller (JTAGC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1663
36.4.1.4 CENSOR_CTRL Register
The CENSOR_CTRL register is a 64-bit shift register path from TDI to TDO selected when the
ENABLE_CENSOR_CTRL instruction is active. The default reset value of the CENSOR_CTRL register
is 64’b0. The CENSOR_CTRL register transfers its value to a parallel hold register on the rising edge of
TCK when the TAP controller state machine is in the Update-DR state. Once the
ENABLE_CENSOR_CTRL instruction is executed, the register value will remain valid until a JTAG reset
occurs.
Figure 36-4. CENSOR_CTRL Register
36.4.1.5 Boundary Scan Register
The boundary scan register is connected between TDI and TDO when the EXTEST, SAMPLE or
SAMPLE/PRELOAD instructions are active. It is used to capture input pin data, force fixed values on
output pins, and select a logic value and direction for bidirectional pins. Each bit of the boundary scan
register represents a separate boundary scan register cell, as described in the IEEE 1149.1-2001 standard
and discussed in
Section 36.5.5, Boundary scan . The size of the boundary scan register and bit ordering is
device-dependent.
11–1
MIC
Manufacturer’s Identification Code
Bits [11:1] contain the JEDEC (Joint Electron Device Engineering Council) manufacturer’s
identification code.
Bit [0] IDCODE Register ID
Bit [0] identifies this register as the device identification register and not the bypass register
*
1
1
The size of CENSOR_CTRL is 64 bits.
... 2 1 0
R
CENSOR_CTRL
W
Reset: *
2
2
The reset value of CENSOR_CTRL is 64’b0.
* * * *
Table 36-6. CENSOR_CTRL register field descriptions
Field Description
63–0
CENSOR_CTRL
[63:0]
Censorship Control
The CENSOR_CTRL bits are used to control chiptop censorship functions.
Table 36-5. Device identification register field descriptions (continued)
Field Description