NXP Semiconductors MPC5644A, Reference Manual, Page: 1526 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
1526 Freescale Semiconductor
33.5.2.75 ECC Error Injection Address Register (FR_EEIAR)
This register defines the memory module, bank, and address where the ECC error has to be injected.
33.5.2.76 ECC Error Injection Data Register (FR_EEIDR)
Table 33-85. FR_EERSR field description
Field Description
CODE Code — The content of this field depends on the report mode selected by FR_EERICR[ERM]
ERM = 0: Syndrome. Shows the ECC syndrome generated by the ECC decoding logic.
The coding of the PE DRAM syndrome is shown in
Section 33.6.24.2.2, PE DRAM syndrome ”
The coding of the CHI LRAM syndrome is shown in Section 33.6.24.2.4, CHI LRAM syndrome ”.
ERM = 1: Checkbits. Shows the ECC checkbits read from the memory.
Base + 0x00FA Write: IDL
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
MID BANK ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 33-106. ECC Error Injection Address Register (FR_EEIAR)
Table 33-86. FR_EEIAR field description
Field Description
MID Memory Identifier — This flag defines the memory instance for ECC error injection.
0 PE DRAM
1 CHI LRAM
BANK Memory Bank — This field defines the memory bank for ECC error injection.
For MID = 0:
000 BANK0: PE DRAM [7:0]
001 BANK1: PE DRAM [15:8]
Others – Reserved
For MID = 1:
000 BANK0: FR_MBCCFR(2n)
001 BANK1: FR_MBFIDR(2n)
010 BANK2: FR_MBIDXR(2n)
011 BANK3: FR_MBCCFR(2n+1)
100 BANK4: FR_MBFIDR(2n+1)
101 BANK5: FR_MBIDXR(2n+1)
Others – Reserved
ADDR Memory Address — This flag defines the memory address for ECC error injection.
Base + 0x00FC Write: IDL
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
DATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 33-107. ECC Error Injection Data Register (FR_EEIDR)