FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
1613
33.6.24.2.4
CHI LRAM syndrome
The coding of the syndrome reported in
ECC Error Report Code Register (FR_EERCR)
for CHI LRAM
33.6.24.3 Memory error response
The memory error response is enabled only when the ECC functionality enable bit ECCE in the
Configuration Register (FR_MCR)
In case of the detection of a
corrected
memory error, the FlexRay module continues its normal operation
using the corrected data word. This section describes the behavior of the FlexRay module after the
detection of a
non-corrected
memory error.
33.6.24.3.1
CHI LRAM memory error response after module read
The FlexRay module reads the message buffer configuration buffer data located in the CHI LRAM for
each message buffer one time in each slot and in the NIT.
If a non-corrected memory error is detected during this module read access, the FlexRay module will
consider the affected message buffer as disabled for the current search and will exclude this buffer from
the search. The configuration of the affected message buffer is not changed.
If the affected message buffer is a tx message buffer, no frame will be transmitted from this message buffer
in the next slot. If the affected message buffer is a rx message buffer, no frame will be received to this
message buffer in the next slot.
33.6.24.3.2
CHI LRAM memory error response after application read
The application can read the content of the CHI LRAM via reading the FR_MBCCFRn, FR_MBFIDRn,
and FR_MBIDXRn registers. If a non-corrected memory error is detected during this kind of read access,
the module indicates the detected memory error, delivers the non-corrected data read and continues its
normal operation.
33.6.24.3.3
PE DRAM error response after module read
If the module detects an non-corrected memory error during read of program data which is contained in
PE DRAM, this is considered as an fatal protocol error and the module enters the protocol freeze state
immediately.
33.6.24.3.4
PE DRAM error response after application read in
POC:default config
state
If the module detects an non-corrected memory error during an application triggered read from any PE
DRAM address and the protocol is in the
POC:default config
state, this is considered as an fatal protocol
Table 33-134. FR_EERCR[CODE] CHI LRAM syndrome coding
FR_EERCR[CODE]
Description
0x00
No Error (Never appears in error report registers)
0x01 – 0x1F
Non-Corrected Error
Summary of Contents for MPC5644A
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