NXP Semiconductors MPC5644A, Reference Manual, Page: 160 / 1735

Enhanced Direct Memory Access Controller (eDMA)
MPC5644A Microcontroller Reference Manual, Rev. 6
160 Freescale Semiconductor
8.3.2.13 eDMA Interrupt Request Registers (EDMA_IRQRH, EDMA_IRQRL)
The EDMA_IRQRH and EDMA_IRQRL provides a bitmap for the 32 channels signaling the presence of
an interrupt request for each channel. EDMA_IRQRH maps to channels 63–32 and EDMA_IRQRL maps
to channels 31–0.
The DMA engine signals the occurrence of a programmed interrupt on the completion of a data transfer
as defined in the transfer control descriptor by setting the appropriate bit in this register. The outputs of
this register are directly routed to the interrupt controller (INTC). During the execution of the interrupt
service routine associated with any given channel, software must clear the appropriate bit, negating the
interrupt request. Typically, a write to the EDMA_CIRQR in the interrupt service routine is used for this
purpose.
The state of any given channel’s interrupt request is directly affected by writes to this register; it is also
affected by writes to the EDMA_CIRQR. On writes to the EDMA_IRQRH or EDMA_IRQRL, a 1 in any
bit position clears the corresponding channel’s interrupt request. A 0 in any bit position has no effect on
the corresponding channel’s current interrupt status. The EDMA_CIRQR is provided so the interrupt
request for a single channel can be cleared without performing a read-modify-write sequence to the
EDMA_IRQRH and EDMA_IRQRL.
Table 8-14. EDMA_CDSBR field descriptions
Field Description
NOP No operation
0 Normal operation
1 No operation, ignore bits 1–7.
CDSB[0:6] Clear DONE Status Bit
0–32 (64 for eDMA) Clear the corresponding channel’s DONE bit.
64–127
Clear all TCD DONE bits.
Address: EDM 0x0020 Access: User R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
INT
6
3
INT
6
2
INT
6
1
INT
6
0
INT
5
9
INT
5
8
INT
5
7
INT
5
6
INT
5
5
INT
5
4
INT
5
3
INT
5
2
INT
5
1
INT
5
0
INT
4
9
INT
4
8
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
INT
4
7
INT
4
6
INT
4
5
INT
4
4
INT
4
3
INT
4
2
INT
4
1
INT
4
0
INT
3
9
INT
3
8
INT
3
7
INT
3
6
INT
3
5
INT
3
4
INT
3
3
INT
3
2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-16. eDMA Interrupt Request High Register (EDMA_IRQRH)