NXP Semiconductors MPC5644A, Reference Manual, Page: 723 / 1735

Reaction Module (REACM)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 723
Figure 23-23. Threshold bank and comparator block diagram
23.4.6 ADC interface
The ADC Interface connects to the eQADC module through a Parallel Side Port also called PSI. Please
refer to
Chapter 25, Enhanced Queued Analog-to-Digital Converter (EQADC) for more information about
this interface. The eQADC sends conversion results to the reaction module which are received by the ADC
interface submodule. The ADC interface is capable of distinguishing between ADC results, Time stamps
and
Prefill information from eQADC. Only ADC results with no Prefill are considered by the reaction
module as valid ADC samples. The TAG value received with the conversion result indicates which
channel the result is addressed to. The ADC interface is also responsible to indicate for the selected
reaction channel that a new ADC result is available. It is also possible to access the ADC interface data
through the REACM_SINR register.
NOTE
The ADC interface data (ADC_TAG and ADC_RESULT) should not be
updated until all reaction channels (with ADCR = ADC_TAG) process the
received data. The OVR flag is set in the case of an overrun condition
occurs, indicating that at least one ADC data was lost.
23.4.6.1 Input buffer overrun
The OVR flag indicates than an input buffer overrun occurred. This buffer is normally written by the ADC
interface (PSI) but can be written also by the CPU using the REACM_SINR register.
The ADC Interface data (ADC_TAG and ADC_RESULT) should not be updated until all Reaction
Channels (with ADCR = ADC_TAG) process the received data. The OVR flag is set in the case of an
adc_data[15:0]
THRESPT[5:0]
comparison
Comparator
.
.
.
Comp
Bank
0
31
Reg
Write
Logic
XBAR Master or eTPU
ADC
Router
on-chip
ADC
Modulation
Control
result
Reaction
channel
Threshold
Bank
modulation addr
COMP
received TAG
4
CHn