NXP Semiconductors MPC5644A, Reference Manual, Page: 1348 / 1735

Enhanced Serial Communication Interface (ESCI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1348 Freescale Semiconductor
Table 31-10. eSCI_IFSR1 field descriptions
Field Description
TDRE Transmit Data Register Empty Interrupt Flag. This interrupt flag is set when the content of the SCI data register
(eSCI_DR) was transferred into internal shift register.
Note: This flag is set in SCI mode only.
TC Transmit Complete Interrupt Flag. This interrupt flag is set when a frame, break or idle character transmission
has been completed and no data were written into
SCI data register (eSCI_DR) after the last setting of the TDRE
flag and the SBK bit in Control register 1 (eSCI_CR1) is 0.
This flag is set in LIN mode, if the preamble was transmitted after the enabling of the transmitter.
RDRF Receive Data Register Full Interrupt Flag. This interrupt flag is set when the payload data of a received frame
was transferred into the
SCI data register (eSCI_DR) and the receive DMA is disabled.
Note: This flag is set in SCI mode only.
IDLE Idle Line Interrupt Flag. This interrupt flag is set when an idle character was detected and the receiver is not in
the wake-up state.
Note: This flag is set in SCI mode only.
OR Overrun Interrupt Flag. This interrupt flag is set when an overrun was detected as described in
Section 31.4.5.3.11, Receiver overrun ”.
Note: This flag is set in SCI mode only.
NF Noise Interrupt Flag. This interrupt flag is set when the receiver has detected noise during the reception of a
frame, as described in
Section 31.4.5.3.13, Bit sampling ”.
FE Framing Error Interrupt Flag. This interrupt flag is set when the payload data of a received frame was transferred
into the
SCI data register (eSCI_DR) or LIN receive register (eSCI_LRR) and the receiver has detected a framing
error during the reception of that frame, as described in Section 31.4.5.3.17, Stop bit verification ”.
PF Parity Error Interrupt Flag. This interrupt flag is set when the payload data of a received frame was transferred
into the
SCI data register (eSCI_DR) and the receiver has detected a parity error for the character, as described
in Section 31.4.5.4, Reception error reporting ”
Note: This flag is set in SCI mode only.
DACT DMA Active. The status bit is set when a transmit or receive DMA request is pending.
0 No DMA request pending
1 DMA request pending.
BERR Bit Error Interrupt Flag. This flag is set when a bit error was detected as described in Section 31.4.6.5.3, Standard
bit error detection ”.
Note: This flag is set in LIN mode only.
WACT LIN Wake-Up Active. The status bit is set as long as the LIN wakeup engine receives a LIN wake-up signal.
0 No LIN wakeup signal reception in progress.
1 LIN wakeup signal reception in progress.
LACT LIN Active. This status bit is set as long as the LIN protocol engine is about to transmit or receive LIN frames.
0 No LIN frame transmission or reception in progress.
1 LIN frame transmission or reception in progress.
TACT Transmitter Active. This status bit is set as long as the transmission of a frame or special character is ongoing.
0 No transmission in progress.
1 Transmission in progress.
RACT Receiver Active. This status bit is set as long as the receive is active. The set and clear conditions for the SCI
mode are described in
Section 31.4.5.3.1, Receiver states and transitions ”.The set and clear conditions for the
LIN mode are described in Section 31.4.6.2.1, LIN byte field reception ”.
0 No reception in progress.
1 Reception in progress.