NXP Semiconductors MPC5644A, Reference Manual, Page: 1382 / 1735

Enhanced Serial Communication Interface (ESCI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1382 Freescale Semiconductor
Figure 31-39. DMA Controlled LIN RX Frame generation and reception
31.4.6.5 LIN error reporting
This section describes error checking and the signaling of detected errors in LIN mode.
31.4.6.5.1 Physical bus error detection
If the receiver input is sampled 0 for at least 31 sample clock cycles after the start of the transmission of a
LIN frame, the physical bus error flag PBERR in the
Interrupt Flag and Status Register 2 (eSCI_IFSR2)
will be set.
31.4.6.5.2 Unrequested activity detection
If an unrequested byte is received (i.e. a byte which is not part of an RX frame) which is not recognized
as a wake-up or break character, the bit error flag BERR in the
Interrupt Flag and Status Register
2 (eSCI_IFSR2) is set. In addition the RXRDY flag will also be set, the LINRX register must be read
before normal operations can proceed.
31.4.6.5.3 Standard bit error detection
The standard bit error detection is enabled when the fast bit error detection control bit FBR in the Control
register 2 (eSCI_CR2) is 0. The standard bit error detection is performed after each LIN byte field
transmission.
During the transmission of the LIN frame header and LIN frame data, the receiver is running and receives
the signal values on the serial bus. After the complete transmission and the related reception of a LIN byte
field, the eSCI compares the data that was transmitted and the data that has been received. If they do not
match, the bit error interrupt flag BERR in the
Interrupt Flag and Status Register 2 (eSCI_IFSR2) is set.
DMA
Controller
eSCI
CSM
TX DMA
channel
ID[5:0] P[1:0]
LEN
1
CSE CRC TD
2
TO[11:8]
DATA 1
DATA 2
DATA N
System Memory
1
LEN must be set to N
2
TD must be set to 0
Break Synch Identifier DATA 1 DATA N Checksum
LIN RX frame
TO[7:0]
RX DMA
channel
from LIN Master from LIN Slave