NXP Semiconductors MPC5644A, Reference Manual, Page: 1122 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
1122 Freescale Semiconductor
25.6.5.2 Distributing Result Data into RFIFOs
Data to be moved into the RFIFOs can come from four sources: from ADC0, from ADC1, from the
external device or from the decimation filter A or B, or reaction module through the PSI. All result data
comes with a MESSAGE_TAG field and a DEST field defining what should be done with the received
data. The EQADC hardware decodes the MESSAGE_TAG and DEST fields and:
• stores the 16-bit data into the appropriate RFIFO if the MESSAGE_TAG indicates a valid RFIFO
number, or;
• sends the 16-bit data, the MESSAGE_TAG and the DEST data through the PSI to decimation filter
A or B or reaction module, or;
• ignores the data in case of a null or “reserved for customer use” MESSAGE_TAG.
In general received data is moved into RFIFOs as they become available, while an exception happens when
multiple results from different sources become available at the same time. In that case, result data from
ADC0 is processed first, result data from ADC1 is only process after all ADC0 data is processed, result
data from the external device is only processed after all data from ADC0/1 is processed, and finally
returned data from companion module is only processed after all data from ADC0/1 and external device
is processed.
When time-stamped results return from the on-chip ADCs, the conversion result and the time stamp are
always moved to the RFIFOs in consecutive clock cycles in order to guarantee they are always stored in
consecutive RFIFO entries.
25.6.6 On-Chip ADC Configuration and Control
25.6.6.1 Enabling and Disabling the On-chip ADCs
The on-chip ADCs have an enable bit (ADC0/1_EN) in the Section 25.5.3.1, ADC0/1 Control Registers
(ADC0_CR and ADC1_CR) , which allows the enabling of the ADCs only when necessary. When the
enable bit for an ADC is negated, the clock input to that ADC is stopped. The ADCs are disabled out of
reset - ADC0/1_EN bits are negated - to allow for their safe configuration. The ADC must only be
configured when its enable bit is negated. Once the enable bit of an ADC is asserted, clock input to is
started.
NOTE
Conversion commands sent to the CBuffer of a disabled ADC are ignored
by the ADC control hardware.
NOTE
A 8ms wait time from VDDA power up to enabling ADC is required to
pre-charge the external 100nf capacitor on REFBYPC pin. This time must
be guaranteed by crystal startup time plus reset duration or user.