NXP Semiconductors MPC5644A, Reference Manual, Page: 1381 / 1735

Enhanced Serial Communication Interface (ESCI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1381
The first data written to the LIN transmit register (eSCI_LTR) provides the Identifier and Identifier Parity
fields. The second data written defines the number of data bytes requested from the LIN slave. The third
data written defines the CRC and checksum generation. The TD bit has to set to 0 to invoke the RX frame
generation. The TO field defines the upper part of the timeout value. The fourth byte written defines the
lower part of the timeout value.
After the fourth byte was written the generation of a LIN RX frame is started. Firstly, a break field is
transmitted, then the synch field and the protected identifier field. After the transmission of the protected
identifier, the eSCI module starts to receive the frame data transmitted by the LIN slave. When the module
has received a complete byte field, the received data are transferred into the
LIN receive register
(eSCI_LRR) and the receive data ready flag RXRDY in the Interrupt Flag and Status Register
2 (eSCI_IFSR2) is set.
The application can retrieve the received data by subsequent read access from LIN receive register
(eSCI_LRR) after checking the RXRDY flag. The application should clear the RXRDY flag immediately
after reading the LIN receive register (eSCI_LRR) .
After the reception of the configured number of data from the slave, the module starts the reception of the
configured CRC and Checksum byte fields. These data are not transferred into the
LIN receive register
(eSCI_LRR) . The CRC and Checksum checking is performed internally. In case of errors, they will be
reported as described in Section 31.4.6.5, LIN error reporting ”
After the reception of the checksum field of the LIN RX frame, the FRC interrupt flag in the Interrupt Flag
and Status Register 2 (eSCI_IFSR2) is set.
31.4.6.4.2 DMA Controlled LIN RX frames generation
In this mode, the eSCI module controls the generation of LIN RX frame header and the reception of the
frame data automatically and utilizes the two connected DMA channels. A block diagram which presents
an overview of the DMA Controlled LIN RX Frame generation and reception is shown in
Figure 31-38 .
The content of the header fields in the memory is the same as described in LIN transmit register
(eSCI_LTR) - LIN RX frame generation . The TX DMA channel is used the fetch the LIN RX frame header
and control information. The RX DMA channel is used to transfer the received frame data into the
memory.
When new data required for transmission, the module generates the transmit DMA request and the DMA
controller delivers the required data. When new data was received, the module generates the receive DMA
request and the DMA controller retrieves the provided data.
The application request the eSCI module to enter this mode by setting the RXDMA bit in the Control
register 2 (eSCI_CR2) . From this point in time, the module start the generation of DMA requests and frame
transmission and reception. Before entering this mode, the application should perform the following
actions:
1. Configure the module for LIN mode.
2. Enable transmitter and receiver by setting TE and RE in Control register 1 (eSCI_CR1) to 1.
3. Setup the two DMA controller channels and provide frame header data in system memory.