NXP Semiconductors MPC5644A, Reference Manual, Page: 1352 / 1735

Enhanced Serial Communication Interface (ESCI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1352 Freescale Semiconductor
31.3.2.9 LIN transmit register (eSCI_LTR)
This register is used by the application to initiate the LIN frame header generation for both LIN TX frames
and LIN RX frames. If a LIN TX frame is generated, this register is used to provide the payload data for
the LIN TX frame.
If the LIN PE is in the idle state (eSCI_LCR[LRES] = 1) or performs a wakeup, each write access to this
register is ignored.
In case of an read access, the register provides the last data written into this register in the DATA field.
If the application initiates a LIN TX frame transfer, i.e the TD bit is set to 1, the content and usage shown
in
LIN transmit register (eSCI_LTR) - LIN TX frame generation applies. The initiation and transmit of a
TX frame is described in Section 31.4.6.3, LIN TX frame generation .
If the application initiates an LIN RX frame, i.e the TD bit is set to 0, the content and usage shown in LIN
transmit register (eSCI_LTR) - LIN RX frame generation applies. The initiation and transmit of a RX
frame is described in Section 31.4.6.4, LIN RX frame generation .
Each successful write access to this register increments the internal write access counter and enables the
writing to the next field. The write access counter is reset if
• the LIN PE is in the idle state (eSCI_LCR[LRES] = 1)
• a LIN TX frame was completely transmitted (eSCI_SR[FRC] was set to 1)
• a LIN RX frame was completely received (eSCI_SR[FRC] was set to 1)
eSC 0x0010 Write: LIN Mode
0 1 2 3 4 5 6 7
R DATA
1st W P ID
2nd W LEN
3rd W CSM CSE CRC TD (=1) TO (ignored)
4th+ W D
Reset 0 0 0 0 0 0 0 0
Figure 31-10. LIN transmit register (eSCI_LTR) - LIN TX frame generation
0 1 2 3 4 5 6 7
R DATA
1st W P[1:0] ID[5:0]
2nd W LEN
3rd W CSM CSE CRC TD (=0) TO[11:8]
4th W TO[7:0]
Reset 0 0 0 0 0 0 0 0
Figure 31-11. LIN transmit register (eSCI_LTR) - LIN RX frame generation