Enhanced Serial Communication Interface (ESCI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
1379
Figure 31-37. CRC Enhanced LIN frame format
The CRC Enhanced LIN frames are not part of the LIN standard.
31.4.6.3
LIN TX frame generation
The eSCI module supports two modes of LIN TX Frame generation, the CPU controlled mode and the
DMA controlled mode. In the CPU controlled mode, the application provides the required frame
configuration and frame data by subsequent CPU write accesses to the
LIN transmit register (eSCI_LTR)
In the DMA controlled mode, the DMA controller provides the required frame configuration and frame
data in response to DMA requests generated by the eSCI module.
31.4.6.3.1
CPU controlled LIN TX frame generation
In this mode, the application initiates the generation of an LIN TX Frame and provides the data to be
transmitted by a sequence of subsequent CPU write accesses to the
LIN transmit register (eSCI_LTR)
When the eSCI module has processed the data written into
LIN transmit register (eSCI_LTR)
, the TXRDY
interrupt flag in the
Interrupt Flag and Status Register 2 (eSCI_IFSR2)
will be set.
The application should clear the TXRDY interrupt flag
before
writing data into the
because the eSCI module will set the TXRDY one clock cycle after the write access.
The first data written to the
LIN transmit register (eSCI_LTR)
provides the Identifier and Identifier Parity
fields. The second data written defines the number of data bytes to be transmitted. The third data written
defines the CRC and checksum generation. The TD bit has to set to 1 in order to invoke the LIN TX frame
generation. The value of the TO field is ignored by the eSCI module for LIN TX frames.
After the third data was written the generation of a LIN TX frame is started. Firstly, a break field is
transmitted, then the synch field and the protected identifier field.
All subsequent write accesses to the
LIN transmit register (eSCI_LTR)
provide data bytes to be transmitted
via the LIN bus. A data byte field will be transmitted as soon as data are available. After the last data byte,
defined by the value written to the LEN field, was send out, the configured CRC and checksum fields will
be send out.
After the transmission of the checksum field of the LIN TX frame, the write access counter for the
is reset and the FRC interrupt flag in the
Interrupt Flag and Status Register
is set.
31.4.6.3.2
DMA Controlled LIN TX frame generation
In this mode, the eSCI module controls the generation of an LIN TX Frame. When new data required for
transmission, the eSCI module generates the transmit DMA request and the DMA controller delivers the
required data. The application request the eSCI module to enter this mode by setting the TXDMA bit in
the
. From this point in time, the module start the generation of DMA
Break
Synch
Identifier
Data 1
Data 2
Data N
Checksum
CRC1
CRC2
Summary of Contents for MPC5644A
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