NXP Semiconductors MPC5644A, Reference Manual, Page: 1179 / 1735

Decimation Filter
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1179
Table 26-4. DECFILTER_MCR Register Field Descriptions
Field Description
0
MDIS
Module Disable. The MDIS bit puts the Decimation Filter in low power mode. Communication
through the PSI slave-bus Interface is ignored in this mode. Writes to the configuration register
are allowed with the exception of writes to the FREN and SRES bits, which are ignored. Writes
to the Coefficient registers are also allowed. The Decimation Filter cannot enter Freeze mode
once in disable mode. Once the module is disabled it no longer receives the system clock.
1 Low Power Mode
0 Normal Mode
1
FREN
Freeze Enable. The FREN bit enables the Decimation Filter to enter freeze mode if the SoC
debug request signal or the FRZ bit is asserted. See
Section 26.5.13, Freeze mode description ,
for more details.
1 Decimation Filter Freeze mode enabled
0 Decimation Filter Freeze mode disabled
2 Reserved, should be cleared.
3
FRZ
Freeze Mode
The FRZ bit controls the freeze mode of the Decimation Filter. For this bit to take effect the FREN
freeze enable bit also needs to be asserted. While in freeze mode the MAC operations are
halted. See
Section 26.5.13, Freeze mode description , for more details.
1 Decimation Filter in Freeze Mode
0 Decimation Filter in Normal Mode
4
SRES
Software-reset bit
The SRES is a self-negated bit which provides the CPU with the capability to initialize the
Decimation Filter through the slave-bus interface. This bit always reads as zero. See
Section 26.5.10, Soft-reset command description , for more details.
1 Software-Reset
0 No action
5–6
CASCD[1:0]
Cascade Mode Configuration. The CASCD[1:0] bit field configures the block to work in cascade
mode of operation according to
Table 26-5 . For more details about the cascade mode, see
Section 26.5.16, Cascade mode description .
Note: Any change to this field must follow the procedure described in the Section 26.5.16.1,
Cascade freeze, stop, and configuration change procedures ”.
IDEN
7
Input Data Interrupt Enable. The IDEN bit enables the Decimation Filter to generate interrupt
requests on all new input data written to the Interface Input Buffer register or Input/Output Buffers
register.
1 Input Data Interrupt Enabled
0 Input Data Interrupt Disabled
Table 26-5. CASCD[1:0] – Filter Cascade mode configuration selection
CASCD[1:0] Description
00 No cascade mode (single block)
01 Cascade Mode, Head block configuration
10 Cascade Mode, Tail block configuration
11 Cascade Mode, Middle block configuration