NXP Semiconductors MPC5644A, Reference Manual, Page: 1218 / 1735

Decimation Filter
MPC5644A Microcontroller Reference Manual, Rev. 6
1218 Freescale Semiconductor
26.5.15.5 Integrator exceptions
Integrator may run into exception states due to overflow, either of the accumulated value or the sample
counter. Exceptions are flagged by the DECFILTER_MXSR bits SSE, for sum value exception, and SCE,
for counter exception. These flags generate an error interrupt, if it is enabled (see
Section 26.5.11.1, Block
interrupt request ”).
The accumulator exception condition depends on whether it operates in saturated mode or not, as follows:
• In Saturated operation (DECFILTER_MXCR bit SSAT = 1): a sum exception occurs (SSE = 1)
whenever an overflow is flagged; SSE asserts together with SSOVF.
• In Non-saturated operation (DECFILTER_MXCR bit SSAT = 0): a sum exception occurs
(SSE = 1) when an overflow is flagged and the DECFILTER_MXSR bit SSOVF is already set to 1.
• In Non-saturated operation, an accumulator exception also occurs if the accumulator overflows
twice without any update of the final integrator value DECFILTER_FINTVAL or the current
integrator counter DECFILTER_CINTCNT (by a read to the DECFILTER_CINTVAL register),
neither an integrator reset occurs. The SSOVF flag does not assert in this situation.
NOTE
The SSOVF flag can only be asserted upon a hardware request, a software
request, or when DECFILTER_CINTVAL is read, based on the internal
accumulator overflow state.
Similarly, the sample counter exception condition depends on whether it operates in saturated mode or not,
as follows:
• In Saturated operation (DECFILTER_MXCR bit SCSAT = 1): a counter exception occurs
(SCE = 1) whenever an overflow is flagged; SCE asserts together with SCOVF.
• In Non-saturated operation (DECFILTER_MXCR bit SCSAT = 0): a counter exception occurs
(SCE = 1) when an overflow is flagged and the DECFILTER_MXSR bit SCOVF is already set to 1.
• In Non-saturated operation, a counter exception also occurs if the counter overflows twice without
any update of the final count DECFILTER_FINTCNT or the current integrator counter
DECFILTER_CINTCNT (by a read to the DECFILTER_CINTVAL register), neither an
integration reset occurs. The SCOVF flag does not assert in this situation.
NOTE
The Scovf Flag Can Only Be Asserted Upon A Hardware Request, A
Software Request, Or When Decfilter_cintval Is Read (Also Updating
Decfilter_cintcnt), Based On The Internal Counter Overflow State.
26.5.16 Cascade mode description
The cascade mode is defined as a configuration mode of the decimation filter to work together with other
ones in a chain arrangement. All blocks in the arrangement, hereafter called a
cascade combo , are
configured to operate in cascade mode by the CASCD[1:0] field in the DECFILTER_MCR. Figure 26-20
shows an example of cascade combo:
• The figure shows PSI being used for both data input and output, but cascade can also work in
standalone or mixed modes.