Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
932
Freescale Semiconductor
24.5.9.1.4
SPRAM access direction
RW field defines the direction of the access in the SPRAM. The access direction is summarized in
.
24.5.9.1.5
Zero SPRAM operation
Zero SPRAM operation is controlled by microcode field ZRO (1 bit). When ZRO field is 0, the data
portion written in SPRAM or in P/DIOB (SPRAM read) registers will always be 0x0. When performing a
Zero SPRAM write operation, the RSIZ is relevant regardless of the P/D field (usually RSIZ is meaningful
only for P/D = 0), which means that zero SPRAM write operation can be performed with 32, 24 or 8 bits
according to SPRAM operation size. These conditions are summarized in
.
NOTE
When field STC is present, STC = 11 also disables Zero SPRAM operation
(see
). The conflicts with DIOB operations (see
Section 24.5.9.1.6, DIOB stack operation
) and ALU operations are resolved
like a normal SPRAM operation (see
).
24.5.9.1.6
DIOB stack operation
SPRAM Indirect Addressing Mode (see
Section , Indirect addressing mode
) is used if STC field (2 bits)
exists in the microinstruction, controlling automatic increment/decrement of DIOB register, as shown in
, thus allowing stack operations. DIOB is incremented and decremented in word addresses,
only from bits 15 downto 2, i.e.: the bits 23 to 16 and 1 to 0 are left untouched by STC pre-decrement and
post-increment.
Table 24-74. SPRAM access direction
R/W
Meaning
0
read SPRAM parameter into P or DIOB registers
1
write SPRAM parameter from P or DIOB registers
Table 24-75. Zero SPRAM operation
ZRO
RW
P/D
Meaning
0
0
0
Clear P register. Size is determined by RSIZ field. See
Section 24.5.9.1.3, SPRAM operation
.
0
0
1
Clear DIOB (all 24 bits), independently of RSIZ
0
1
x
Clear SPRAM parameter. Size is determined by RSIZ field. See
.
1
RW
P/D Regular SPRAM operation
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