NXP Semiconductors MPC5644A, Reference Manual, Page: 149 / 1735

Enhanced Direct Memory Access Controller (eDMA)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 149
8.3.2.2 eDMA Error Status Register (EDMA_ESR)
The EDMA_ESR provides information about the last recorded channel error. Channel errors can be caused
by a configuration error (an illegal setting in the transfer control descriptor or an illegal priority register
setting in fixed-arbitration mode) or an error termination to a bus master read or write cycle.
A configuration error is caused when the starting source or destination address, source or destination
offsets, minor loop byte count, and the transfer size represent an inconsistent state. The addresses and
offsets must be aligned on 0-modulo-transfer_size boundaries, and the minor loop byte count must be a
multiple of the source and destination transfer sizes. All source reads and destination writes must be
configured to the natural boundary of the programmed transfer size respectively.
In fixed-arbitration mode, a configuration error is generated when any two channel priority levels are equal
and any channel is activated. The ERRCHN field is undefined for this type of error. All channel priority
levels must be unique before any service requests are made.
If a scatter-gather operation is enabled on channel completion, a configuration error is reported if the
scatter-gather address (DLAST_SGA) is not aligned on a 32-byte boundary. If minor loop channel linking
is enabled on channel completion, a configuration error is reported when the link is attempted if bit
EDMA_TCD[CITER.E_LINK] is not equal to bit EDMA_TCD[BITER.E_LINK]. All configuration error
CLM Continuous link mode
0 A minor loop channel link made to itself goes through channel arbitration before being activated
again.
1 A minor loop channel link made to itself does not go through channel arbitration before being
activated again. Upon minor loop completion, the channel is active again if that channel has a
minor loop channel link enabled and the link channel is itself. This effectively applies the minor
loop offsets and restarts the next minor loop.
HALT Halt DMA operations
0 Normal operation
1 Stall the start of any new channels. Executing channels are allowed to complete. Channel
execution resumes when the HALT bit is cleared.
HOE Halt on error
0 Normal operation
1 Any error causes the HALT bit to be set. Subsequently, all service requests are ignored until the
HALT bit is cleared.
ERGA Enable round-robin group arbitration
0 Fixed-priority arbitration is used for selection among the groups.
1 Round-robin arbitration is used for selection among the groups.
ERCA Enable Round-Robin Channel Arbitration
0 Fixed-priority arbitration is used for channel selection within each group.
1 Round-robin arbitration is used for channel selection within each group.
EDBG Enable Debug
0 The assertion of the system debug control input is ignored.
1 The assertion of the system debug control input causes the eDMA to stall the start of a new
channel. Executing channels are allowed to complete. Channel execution resumes when either
the system debug control input is negated or the EDBG bit is cleared.
Table 8-3. EDMA_CR field descriptions (continued)
Field Description