NXP Semiconductors MPC5644A, Reference Manual, Page: 1628 / 1735

Periodic Interrupt Timer (PIT)
MPC5644A Microcontroller Reference Manual, Rev. 6
1628 Freescale Semiconductor
34.4.2.1 PIT Module Control Register (PITMCR)
This register controls whether the timer clocks should be enabled and whether the timers should run in
debug mode.
34.4.2.2 Timer Load Value Register n (LDVALn)
These registers select the timeout period for the timer interrupts. In the case of the RTI, it will take several
cycles until this value is synchronized into the RTI clock domain. For all other timers the value change is
visible immediately. The synchronization mechanism allows 0 wait states in this case.
Offset 0x000 Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0
MDIS
_RTI
MDIS FRZ
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 34-2. PIT Module Control Register (PITMCR)
Table 34-3. PITMCR field descriptions
Field Description
MDIS_RTI Module Disable—RTI section
This is used to disable the RTI timer. This bit should be enabled before any RTI setup is done.
0: Clock for RTI is enabled (default)
1: Clock for RTI disabled
MDIS Module Disable—PIT section
This is used to disable the standard timers. The RTI timer is not affected by this bit. This bit should be
enabled before any other setup is done.
0: Clock for PIT Timers is enabled (default)
1: Clock for PIT Timers is disabled
FRZ Freeze
Allows the timers to be stopped when the device enters debug mode.
0: Timers continue to run in debug mode.
1: Timers are stopped in debug mode.