Enhanced Direct Memory Access Controller (eDMA)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
147
Many of the control registers have a bit width that matches the number of channels implemented in the
module:
•
64 bits for eDMA (made up of two 32-bit registers: high and low—for example, EDMA_ERQRH
has upper 32 channels of eDMA)
8.3.2.1
eDMA Control Register (EDMA_CR)
The 32-bit EDMA_CR defines the basic operating configuration of the eDMA.
The eDMA arbitrates channel service requests in four (eDMA) groups (0, 1, 2, 3) of 16 channels each:
•
Group 0 contains channels 0–15
•
Group 1 contains channels 16–31
•
Group 2 contains channels 32–47 (eDMA only)
•
Group 3 contains channels 48–63 (eDMA only)
Arbitration within a group can be configured to use a fixed priority or a round robin. In fixed-priority
arbitration, the highest priority channel requesting service is selected to execute. The priorities are
assigned by the channel priority registers. See
Section 8.3.2.16, eDMA Channel n Priority Registers
In round-robin arbitration mode, the channel priorities are ignored and the channels
within each group are cycled through, from channel 15 down to channel 0,without regard to priority.
The group priorities operate in a similar fashion. In group fixed-priority arbitration mode, channel service
requests in the highest priority group are executed first where priority level 3 (eDMA) is the highest and
priority level 0 is the lowest. The group priorities are assigned in the GRP
n
PRI fields of the eDMA control
register (EDMA_CR). All group priorities must have unique values prior to any channel service requests
occur, otherwise a configuration error is reported. In group round-robin mode, the group priorities are
ignored and the groups are cycled through, from group 3 (eDMA) down to group 0, without regard to
priority.
Minor loop offsets are address offset values added to the final source address (SADDR) or destination
address (DADDR) upon minor loop completion. When minor loop offsets are enabled, the minor loop
offset (MLOFF) is added to the final source address (SADDR) or to the final destination address
(DADDR) or to both addresses prior to the addresses being written back into the TCD. If the major loop
is complete, the minor loop offset is ignored and the major loop address offsets (SLAST and
DLAST_SGA) are used to compute the next EDMA_TCD[SADDR] and EDMA_TCD[DADDR] values.
When minor loop mapping is enabled (EDMA_CR[EMLM] = 1), TCD
n
word2 is redefined. A portion of
TCD
n
word2 is used to specify multiple fields: a source enable bit (SMLOE) to specify that the minor loop
offset should be applied to the source address (SADDR) upon minor loop completion, a destination enable
bit (DMLOE) to specify the minor loop offset should be applied to the destination address (DADDR) upon
minor loop completion, and the sign extended minor loop offset value (MLOFF). The same offset value
(MLOFF) is used for both source and destination minor loop offsets.
When either of the minor loop offsets is enabled (SMLOE is set or DMLOE is set), the NBYTES field is
reduced to 10 bits. When both minor loop offsets are disabled (SMLOE is cleared and DMLOE is cleared),
the NBYTES field becomes a 30-bit vector.
Summary of Contents for MPC5644A
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Page 1228: ...Decimation Filter MPC5644A Microcontroller Reference Manual Rev 6 1228 Freescale Semiconductor...
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