NXP Semiconductors MPC5644A, Reference Manual, Page: 1147 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1147
Figure 25-88. Slave Driving the MSB and Consecutive Bits in a Data Transmission
SDS is asserted after positive edge of FCK.
Slave drives second bit due to detection of
an asserted SDS on the negative edge of
FCK.
Master’s SDI
25 26 1 2 3 ...
25 26 1 2 3 ...
25 26 1 1 2 3 ...
SDS
FCK
Slave Sample
Input
t
DT
t
DT
t
DT
Begin
Transmission
Begin
Transmission
Begin
Transmission
End
Transmission
End
Transmission
SDS is asserted before positive edge of
FCK. Slave drives second bit due to
detection of an asserted SDS on the
negative edge of FCK.
Slave drives MSB bit again due to detection
of a negated SDS on the negative edge of
FCK.
(1)
(2)
(3)
Master’s SDI
SDS
FCK
Slave Sample
Input
Master’s SDI
SDS
FCK
Slave Sample
Input
End
Transmission