NXP Semiconductors MPC5644A, Reference Manual, Page: 1261 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1261
Table 30-4. DSPI_MCR field description
Field Description
0
MSTR
Master/Slave Mode Select
The MSTR bit configures the DSPI for either master mode or slave mode.
0 DSPI is in slave mode
1 DSPI is in master mode
1
CONT_SCK
E
Continuous SCK Enable
The CONT_SCKE bit enables the Serial Communication Clock (SCK) to run continuously. See
Section 30.9.7, Continuous serial communications clock , for details.
0 Continuous SCK disabled
1 Continuous SCK enabled
2–3
DCONF[0:1]
DSPI Configuration
The DCONF field selects between the three different configurations of the DSPI:
00 SPI
01 DSI
10 CSI
11 Reserved
4
FRZ
Freeze
The FRZ bit enables the DSPI transfers to be stopped on the next frame boundary when the device
enters Debug mode.
0 Do not stop serial transfers
1 Stop serial transfers
5
MTFE
Modified Timing Format Enable
The MTFE bit enables a modified transfer format to be used. See
Section 30.9.6.4, Modified SPI/DSI
transfer format (MTFE = 1, CPHA = 1) , for more information.
0 Modified SPI transfer format disabled
1 Modified SPI transfer format enabled
6
PCSSE
Peripheral Chip Select Strobe Enable
The PCSSE bit enables the DSPI_x_PCS[5]/PCSS to operate as a PCS Strobe output signal. See
Section 30.9.5.5, Peripheral chip select strobe enable (PCSS) , for more information.
0 DSPI_x_PCS[5]/PCSS is used as the Peripheral Chip Select[5] signal
1 DSPI_x_PCS[5]/PCSS is used as an active-low PCS Strobe signal
7
ROOE
Receive FIFO Overflow Overwrite Enable
The ROOE bit enables in RX FIFO overflow condition to ignore the incoming serial data or to
overwrite existing data. If the RX FIFO is full and new data is received, the data from the transfer,
generated the overflow, is ignored or shifted in to the shift register. See
Section 30.9.10.6, Receive
FIFO overflow interrupt request , for more information.
0 Incoming data is ignored
1 Incoming data is shifted in to the shift register
8–15
PCSIS x
Peripheral Chip Select Inactive State
The PCSIS bit determines the inactive state of the PCS
x signal.
0 The inactive state of PCS x is low
1 The inactive state of PCS x is high
17
MDIS
Module Disable
The MDIS bit allows the clock to be stopped to the non-memory mapped logic in the DSPI effectively
putting the DSPI in a software controlled power-saving state. See
Section 30.9.18, Power saving
features , for more information. The reset value of the MDIS bit is parameterized, with a default reset
value of ‘0’.
0 Enable DSPI clocks.
1 Allow external logic to disable DSPI clocks.